diff mbox

[v2,1/2] dt-bindings: Add bindings for nvidia, tegra186-ccplex-cluster

Message ID 1496304245-24024-2-git-send-email-mperttunen@nvidia.com
State Not Applicable, archived
Headers show

Commit Message

Mikko Perttunen June 1, 2017, 8:04 a.m. UTC
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt        | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt

Comments

Rob Herring (Arm) June 7, 2017, 10:11 p.m. UTC | #1
On Thu, Jun 01, 2017 at 11:04:04AM +0300, Mikko Perttunen wrote:
> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
> registers that initiate CPU frequency/voltage transitions.

What the block is should also go in the binding doc. With that,

Acked-by: Rob Herring <robh@kernel.org>

> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---
>  .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt        | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
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Mikko Perttunen June 8, 2017, 7:32 a.m. UTC | #2
On 08.06.2017 01:11, Rob Herring wrote:
> On Thu, Jun 01, 2017 at 11:04:04AM +0300, Mikko Perttunen wrote:
>> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
>> registers that initiate CPU frequency/voltage transitions.
>
> What the block is should also go in the binding doc. With that,

I don't know how to explain it in more detail; this thing is literally 
just a few magic registers that route into some CPU control logic to 
trigger frequency/voltage transitions :)

Mikko

>
> Acked-by: Rob Herring <robh@kernel.org>
>
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> ---
>>  .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt        | 17 +++++++++++++++++
>>  1 file changed, 17 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
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Rob Herring (Arm) June 9, 2017, 8:54 p.m. UTC | #3
On Thu, Jun 8, 2017 at 2:32 AM, Mikko Perttunen <cyndis@kapsi.fi> wrote:
> On 08.06.2017 01:11, Rob Herring wrote:
>>
>> On Thu, Jun 01, 2017 at 11:04:04AM +0300, Mikko Perttunen wrote:
>>>
>>> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
>>> registers that initiate CPU frequency/voltage transitions.
>>
>>
>> What the block is should also go in the binding doc. With that,
>
>
> I don't know how to explain it in more detail; this thing is literally just
> a few magic registers that route into some CPU control logic to trigger
> frequency/voltage transitions :)

Copy the commit msg text to the binding doc. That's all I'm asking for.

Rob
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Mikko Perttunen June 12, 2017, 8:25 a.m. UTC | #4
On 09.06.2017 23:54, Rob Herring wrote:
> On Thu, Jun 8, 2017 at 2:32 AM, Mikko Perttunen <cyndis@kapsi.fi> wrote:
>> On 08.06.2017 01:11, Rob Herring wrote:
>>>
>>> On Thu, Jun 01, 2017 at 11:04:04AM +0300, Mikko Perttunen wrote:
>>>>
>>>> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
>>>> registers that initiate CPU frequency/voltage transitions.
>>>
>>>
>>> What the block is should also go in the binding doc. With that,
>>
>>
>> I don't know how to explain it in more detail; this thing is literally just
>> a few magic registers that route into some CPU control logic to trigger
>> frequency/voltage transitions :)
>
> Copy the commit msg text to the binding doc. That's all I'm asking for.
>
> Rob
>

I see. Will do, thanks.

Mikko
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
new file mode 100644
index 000000000000..e8fb416c892b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
@@ -0,0 +1,17 @@ 
+NVIDIA Tegra CCPLEX_CLUSTER area
+
+Required properties:
+- compatible: Should contain one of the following:
+  - "nvidia,tegra186-ccplex-cluster": for Tegra186
+- reg: Must contain an (offset, length) pair of the device's MMIO
+  register area
+- nvidia,bpmp: phandle to BPMP device that can be queried for OPP tables
+
+Example:
+
+	ccplex@e000000 {
+		compatible = "nvidia,tegra186-ccplex-cluster";
+		reg = <0x0 0x0e000000 0x0 0x3fffff>,
+
+		nvidia,bpmp = <&bpmp>;
+	};