From patchwork Tue Apr 18 01:17:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 751604 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3w6S1C4FN7z9s0g for ; Tue, 18 Apr 2017 11:17:51 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="FSXXMmw4"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754971AbdDRBRu (ORCPT ); Mon, 17 Apr 2017 21:17:50 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:36796 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753721AbdDRBRt (ORCPT ); Mon, 17 Apr 2017 21:17:49 -0400 Received: by mail-pf0-f176.google.com with SMTP id 194so33735002pfv.3 for ; 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Mon, 17 Apr 2017 18:17:48 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.92]) by smtp.gmail.com with ESMTPSA id t5sm20163049pgb.58.2017.04.17.18.17.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Apr 2017 18:17:47 -0700 (PDT) From: Zhangfei Gao To: Stephen Boyd , Rob Herring , guodong Xu , xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao , Li Pengcheng Subject: [PATCH 1/2] clk: hi6220: add acpu clock Date: Tue, 18 Apr 2017 09:17:21 +0800 Message-Id: <1492478242-16146-1-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: Zhangfei Gao Signed-off-by: Li Pengcheng Acked-by: Rob Herring Acked-by: Wei Xu --- .../devicetree/bindings/clock/hi6220-clock.txt | 1 + drivers/clk/hisilicon/clk-hi6220.c | 23 ++++++++++++++++++++++ include/dt-bindings/clock/hi6220-clock.h | 4 ++++ 3 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt index e4d5fea..ef3deb7 100644 --- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt +++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt @@ -11,6 +11,7 @@ Required Properties: - compatible: the compatible should be one of the following strings to indicate the clock controller functionality. + - "hisilicon,hi6220-acpu-sctrl" - "hisilicon,hi6220-aoctrl" - "hisilicon,hi6220-sysctrl" - "hisilicon,hi6220-mediactrl" diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 2ae151c..fc8813f 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -285,3 +285,26 @@ static void __init hi6220_clk_power_init(struct device_node *np) ARRAY_SIZE(hi6220_div_clks_power), clk_data); } CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init); + + +/* clocks in acpu */ +static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = { + { HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, }, +}; + +static void __init hi6220_clk_acpu_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks, + ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), + clk_data); +} + +CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init); diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index b8ba665..409cc02 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -174,4 +174,8 @@ #define HI6220_DDRC_AXI1 7 #define HI6220_POWER_NR_CLKS 8 + +/* clk in Hi6220 acpu sctrl */ +#define HI6220_ACPU_SFT_AT_S 0 + #endif