From patchwork Wed Nov 2 14:37:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 690423 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t89lG4hkYz9vDY for ; Thu, 3 Nov 2016 01:41:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=aj.id.au header.i=@aj.id.au header.b=JV6gB2KX; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b=rS1hGbqj; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755784AbcKBOjg (ORCPT ); Wed, 2 Nov 2016 10:39:36 -0400 Received: from out2-smtp.messagingengine.com ([66.111.4.26]:35586 "EHLO out2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754423AbcKBOje (ORCPT ); Wed, 2 Nov 2016 10:39:34 -0400 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 0917620814; Wed, 2 Nov 2016 10:39:33 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute7.internal (MEProxy); Wed, 02 Nov 2016 10:39:33 -0400 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=aj.id.au; h= x-me-sender:x-sasl-enc:from:to:cc:subject:date:message-id :in-reply-to:references; s=mesmtp; bh=ihDSh646EQasrFHE2RIxU9kQ/Y 0=; b=JV6gB2KXnFziVtq4BSKu9Rn2vaYjjo9ERri/A/ZgnUrK3wWENrqe2PyoUV /GWdP7UWQ/X/zHudqUBlIfsikH68nMLcJH9Vz99u3Iat9Sn6eGRaJ5SOMqHM3ziB n9TtWtkHysQvoEiw+iKabzCp7QL50EPKE4hdNs8tF0m23+9xY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=x-me-sender:x-sasl-enc:from:to:cc:subject :date:message-id:in-reply-to:references; s=smtpout; bh=ihDSh646E QasrFHE2RIxU9kQ/Y0=; b=rS1hGbqjH9fkLoCzK5Bl7odVLr0x/q8ICEAYhAuSg jDuoZtwC4FzSkp4rIEsbfoDwABuZxmSwGo/v4OKJELsidncMPWU9W+7fwacKV6zY lw2/n0yUCs3lp5GvMubO7vMY4Ofzrpou1djqp3V8wN7T5W4aWO6QhmwaG8oetbis Xc= X-ME-Sender: X-Sasl-enc: Pi3kcBOBG/EGJ2LE5q/a/S98kDBActHa+szxF3O9Gek0 1478097571 Received: from keelia.au.ibm.com (ppp203-122-213-247.static.internode.on.net [203.122.213.247]) by mail.messagingengine.com (Postfix) with ESMTPA id 6909BCCF29; Wed, 2 Nov 2016 10:39:26 -0400 (EDT) From: Andrew Jeffery To: Lee Jones , Linus Walleij Cc: Joel Stanley , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Andrew Jeffery Subject: [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Date: Thu, 3 Nov 2016 01:07:57 +1030 Message-Id: <1478097481-14895-3-git-send-email-andrew@aj.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au> References: <1478097481-14895-1-git-send-email-andrew@aj.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Aspeed SoC Display Controller is presented as a syscon device to arbitrate access by display and pinmux drivers. Video pinmux configuration on fifth generation SoCs depends on bits in both the System Control Unit and the Display Controller. Signed-off-by: Andrew Jeffery Acked-by: Rob Herring --- Documentation/devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt new file mode 100644 index 000000000000..aea5370efd97 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt @@ -0,0 +1,17 @@ +* Device tree bindings for Aspeed SoC Display Controller (GFX) + +The Aspeed SoC Display Controller primarily does as its name suggests, but also +participates in pinmux requests on the g5 SoCs. It is therefore considered a +syscon device. + +Required properties: +- compatible: "aspeed,ast2500-gfx", "syscon" +- reg: contains offset/length value of the GFX memory + region. + +Example: + +gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; +};