From patchwork Tue Oct 4 15:08:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 678135 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3spMkS715zz9t1F for ; Wed, 5 Oct 2016 02:08:48 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=pjGjYlNo; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753108AbcJDPIr (ORCPT ); Tue, 4 Oct 2016 11:08:47 -0400 Received: from mail-lf0-f45.google.com ([209.85.215.45]:34378 "EHLO mail-lf0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752652AbcJDPIr (ORCPT ); Tue, 4 Oct 2016 11:08:47 -0400 Received: by mail-lf0-f45.google.com with SMTP id b81so67704096lfe.1 for ; Tue, 04 Oct 2016 08:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nU7aJGGpnujC4rLHWrrZrquuIeSX7HQI+rTzJmOWXuM=; b=pjGjYlNoTOdGanNWqNHvTKLcUI/lJMzeFJicmBSlLIMfOPNqToG7KuXa9kYaZeIYZj //n0TwngQcvkQSqF4A1wkw7hbuOGX8zUuzWeiPPtuA+auwPFP04uUqDgklQGuTDOX/7T ELXW7mUa18VSGrjDo+Yb85KgrEpOn6wRppDAJkag/R84HBS1QZaWb5aoV+/S3KrPEvzG yH3xOWrx8D+2OBcQiTo/BTgk7plNRxZsPn6jEPAno9XOGT82kYFWs6Wu4QqK6b9fa/au mOjc0uTswuN6ts/MpDbgWT/q1o7VxjgfCKYdCpIF8BpzbQURjU0v1n07VtzQRFGKbnmS pydg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nU7aJGGpnujC4rLHWrrZrquuIeSX7HQI+rTzJmOWXuM=; b=fRytLnQJ4UcT9G/ukcU53pNOQLtejaVe7D5EF98LGyKq7RRDfauGkU9PKPbyzDJJdw ukjQovJiC4wCvY+rs6GbAkWS8vwCN2iUi9uvrH+ZnRLiD9Gtgzk4TEa8iO6SRqi8CI15 nfislLtbL8/fFf/Nop43Vg8eAFhv4IWxbcF4AyqfEyPFpSR2fDENFSVSgSmdkiF1kHv2 p6qoC7cQosRswd3O3AuNMirGIOhQ9ecbBoC5TIXPpNAFiyWMYwRlB2SPSxrOO45PjBGC rmQj2Ek2+dK1roW8VyOaP8t+HG+8VyTuDWMXDnjxu4fQqUAcfk2xZqejaYEB7grRnydB rDpA== X-Gm-Message-State: AA6/9Rm2eh/IeUiUYMUmQfp+/fHlfyetpDmWodwswhB91jdW5oypl1DoM8CSzKIIneROvGVJ X-Received: by 10.194.175.106 with SMTP id bz10mr3436872wjc.42.1475593724981; Tue, 04 Oct 2016 08:08:44 -0700 (PDT) Received: from boomer.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id j198sm4583539wmg.4.2016.10.04.08.08.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Oct 2016 08:08:44 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman , Carlo Caione , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [RFC 02/10] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller Date: Tue, 4 Oct 2016 17:08:20 +0200 Message-Id: <1475593708-10526-3-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1475593708-10526-1-git-send-email-jbrunet@baylibre.com> References: <1475593708-10526-1-git-send-email-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds the device tree bindings description for Amlogic's GPIO interrupt controller available on the meson8, meson8b and gxbb SoC families Signed-off-by: Jerome Brunet Acked-by: Rob Herring --- .../amlogic,meson-gpio-intc.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt new file mode 100644 index 000000000000..bd4cceefcda1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -0,0 +1,39 @@ +Amlogic meson GPIO interrupt controller + +Meson SoCs contains an interrupt controller which is able watch the SoC pads +and generate an interrupt on edges or level. The controller is essentially a +256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. We don’t expose all 256 mux inputs because the +documentation shows that upper part is not mapped to any pad. The actual number +of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : should be: "amlogic,meson8-gpio-intc” or + “amlogic,meson8b-gpio-intc” or “amlogic,gxbb-gpio-intc” +- interrupts : List of the GIC’s interrupts used as parent interrupts. + There should 8 of these interrupts. +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + +Exemple: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,gxbb-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; +};