From patchwork Sat Sep 10 02:15:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 668332 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sWHk72FgLz9sxN for ; Sat, 10 Sep 2016 12:16:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753083AbcIJCP7 (ORCPT ); Fri, 9 Sep 2016 22:15:59 -0400 Received: from mail-pa0-f65.google.com ([209.85.220.65]:36390 "EHLO mail-pa0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753061AbcIJCP4 (ORCPT ); Fri, 9 Sep 2016 22:15:56 -0400 Received: by mail-pa0-f65.google.com with SMTP id ez1so4557826pab.3; Fri, 09 Sep 2016 19:15:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dp1IOju7hXbryq2GExOanCBeOvdrEQ0mn9eH7uSBV58=; b=OaDfUJ85nlr7Xp8ItK7fMeFyJmg0KoqQq+rWRXWn2t8TJfRA3UdGXBxAFY3pA3rpnY gsXUN2FiVaou037Jfxx75UpPjBn3OHMPxAJq2vVhKPcOvekFY2LE2Fw3CYcFl7Cff++F AdYTUL3kr2eIPRVVNoOvS+WrmqiIC80R3SSL2LLUGTPA7u1eTo/gKQgqrzaSV+dWrZ10 QOEgfj9YXTWTfOCO8UsBPM5o9QvBzkZnK/GmTRh9HHXGh1g8MI9gZIPv59YmLSXPWk76 6pb93HoI28Hvjw/umVoLDkZUoB9joHpNnK0xP/7uEgTBEp4rkNENFB3CYIfwKWaFU25o ytxg== X-Gm-Message-State: AE9vXwMHpEptJSjxENWfUAKuQ+loeyKCkbIfwCCB4+zr5xR+I34dauPJvAlexLv+dVKiNA== X-Received: by 10.66.50.99 with SMTP id b3mr12265673pao.28.1473473755902; Fri, 09 Sep 2016 19:15:55 -0700 (PDT) Received: from user5-HP-Z620-Workstation.corp.google.com ([172.22.52.170]) by smtp.gmail.com with ESMTPSA id p4sm8006029pfp.60.2016.09.09.19.15.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Sep 2016 19:15:55 -0700 (PDT) From: Chris Zhong To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de, yzq@rock-chips.com, groeck@chromium.org, myungjoo.ham@samsung.com, cw00.choi@samsung.com, wulf@rock-chips.com, marcheu@chromium.org, briannorris@chromium.org, zhengxing@rock-chips.com, cychiang@chromium.org, hychao@chromium.org, broonie@kernel.org Cc: linux-rockchip@lists.infradead.org, Chris Zhong , devicetree@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Ian Campbell , Rob Herring , Pawel Moll , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v15 2/5] Documentation: bindings: add dt documentation for cdn DP controller Date: Fri, 9 Sep 2016 19:15:45 -0700 Message-Id: <1473473748-22331-3-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1473473748-22331-1-git-send-email-zyw@rock-chips.com> References: <1473473748-22331-1-git-send-email-zyw@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring Reviewed-by: Guenter Roeck --- Changes in v15: None Changes in v14: None Changes in v13: - add dptx and apb reset Changes in v12: None Changes in v11: - refer dp phy Changes in v10: - add pclk_vio_grf clock Changes in v9: - modify the reference phy = <&tcphy0 0>, <&tcphy1 0>; Changes in v8: None Changes in v7: None Changes in v6: - add assigned-clocks and assigned-clock-rates - add power-domains Changes in v5: None Changes in v4: - add a reset node - support 2 phys Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2: None Changes in v1: - add extcon node description - add #sound-dai-cells description .../bindings/display/rockchip/cdn-dp-rockchip.txt | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt new file mode 100644 index 0000000..9bd2c13 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt @@ -0,0 +1,75 @@ +Rockchip RK3399 specific extensions to the cdn Display Port +================================ + +Required properties: +- compatible: must be "rockchip,rk3399-cdn-dp" + +- reg: physical base address of the controller and length + +- clocks: from common clock binding: handle to dp clock. + +- clock-names: from common clock binding: + Required elements: "core-clk" "pclk" "spdif" "grf" + +- resets : a list of phandle + reset specifier pairs +- reset-names : string reset name, must be: + "spdif", "dptx", "apb". +- power-domains : power-domain property defined with a phandle + to respective power domain. +- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> +- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 + +- rockchip,grf: this soc should set GRF regs, so need get grf here. + +- ports: contain a port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + contained 2 endpoints, connecting to the output of vop. + +- phys: from general PHY binding: the phandle for the PHY device. + +- extcon: extcon specifier for the Power Delivery + +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF + +------------------------------------------------------------------------------- + +Example: + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>; + reset-names = "spdif", "dptx", "apb"; + extcon = <&fusb0>, <&fusb1>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + };