From patchwork Tue Jul 12 15:09:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 647449 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rplmZ707Qz9s65 for ; Wed, 13 Jul 2016 01:11:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933566AbcGLPL0 (ORCPT ); Tue, 12 Jul 2016 11:11:26 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:36005 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933469AbcGLPKQ (ORCPT ); Tue, 12 Jul 2016 11:10:16 -0400 Received: by mail-pf0-f196.google.com with SMTP id i123so1247777pfg.3; Tue, 12 Jul 2016 08:10:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VWLun0p/J1ZdRzImFY7OJBPTIN2cIaN00VBWWMydlOQ=; b=FGVRqqGqQsRnEpuhODVR+vORpL8CdU8GyS9NUQW2MvuaKiIH7Zz7os73EVdYsnyQFr F3MTk5jAhvjAFpNdWpCtWizOFL5KK6MgtOiGUae62h1c65yvZBmtC6HnCI1UjIhNgcI+ eDPObY/flQRO0cAJmDQQaQiVZBCt+shXYuJWE3cwhiHjeZqMTajbNR2TWcwtusZFg2Me Xqup6hw/TcJtMj/QOhTRiyT/bvrOwe8WjdnUF6DoJff60ys37qH56GkbZe0eDSfdPbod R4lJHGGN5v+AICWWGde4RvFyYOcfRSHGqXoDOzWMEhEiqHBx797KBwgPlg6k6cUN82eQ 7Qng== X-Gm-Message-State: ALyK8tIc7IHjkH/PhJfezwtd8gVpJjznNrUh7VTIF4TSCxExz+JJQE5lhArG/Vf6hsh5rA== X-Received: by 10.98.6.132 with SMTP id 126mr45461670pfg.109.1468336215894; Tue, 12 Jul 2016 08:10:15 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id s12sm3702800pfj.57.2016.07.12.08.10.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jul 2016 08:10:14 -0700 (PDT) From: Chris Zhong To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de, yzq@rock-chips.com, groeck@chromium.org, myungjoo.ham@samsung.com, cw00.choi@samsung.com, wulf@rock-chips.com, marcheu@chromium.org Cc: linux-rockchip@lists.infradead.org, Chris Zhong , Mark Yao , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [v5 PATCH 4/5] Documentation: bindings: add dt documentation for cdn DP controller Date: Tue, 12 Jul 2016 23:09:47 +0800 Message-Id: <1468336188-565-5-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1468336188-565-1-git-send-email-zyw@rock-chips.com> References: <1468336188-565-1-git-send-email-zyw@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v5: None Changes in v4: - add a reset node - support 2 phys Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2: None Changes in v1: - add extcon node description - add #sound-dai-cells description .../bindings/display/rockchip/cdn-dp-rockchip.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt new file mode 100644 index 0000000..bf0b2ce --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt @@ -0,0 +1,67 @@ +Rockchip RK3399 specific extensions to the cdn Display Port +================================ + +Required properties: +- compatible: must be "rockchip,rk3399-cdn-dp" + +- reg: physical base address of the controller and length + +- clocks: from common clock binding: handle to dp clock. + +- clock-names: from common clock binding: + Required elements: "core-clk" "pclk" "spdif" + +- resets : a list of phandle + reset specifier pairs +- reset-names : string reset name, must be: + "spdif" + +- rockchip,grf: this soc should set GRF regs, so need get grf here. + +- ports: contain a port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + contained 2 endpoints, connecting to the output of vop. + +- phys: from general PHY binding: the phandle for the PHY device. + +- extcon: extcon specifier for the Power Delivery + +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF + +------------------------------------------------------------------------------- + +Example: + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>; + clock-names = "core-clk", "pclk", "spdif"; + phys = <&tcphy0>, <&tcphy1>; + resets = <&cru SRST_DPTX_SPDIF_REC>; + reset-names = "spdif"; + extcon = <&fusb0>, <&fusb1>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + };