From patchwork Mon Jun 20 17:56:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 638214 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rYKFl3Nb6z9t0X for ; Tue, 21 Jun 2016 04:31:55 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b=mdqO0Fxr; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754595AbcFTSbc (ORCPT ); Mon, 20 Jun 2016 14:31:32 -0400 Received: from mail-pf0-f169.google.com ([209.85.192.169]:34383 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754633AbcFTSba (ORCPT ); Mon, 20 Jun 2016 14:31:30 -0400 Received: by mail-pf0-f169.google.com with SMTP id h14so41325914pfe.1 for ; Mon, 20 Jun 2016 11:30:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ap8C1YE9ACbQLrn/VIl/umq56cpRNHWFTM2op5N88ps=; b=mdqO0Fxr7g9IXprGtRLJAF5nYojEqS7NDXYsD70yrZnA7dU41rAhCuf4LrFEIxjJz5 NZ3zrcoaYt2V35XekxFDTYdBCmhbXCAPaH2FTyLF+DIvp9QIkzw204gW08x6LjTFycfF Le+P5c6WpadQ57lwZL+ElWwxY5db1jjMNBeNM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ap8C1YE9ACbQLrn/VIl/umq56cpRNHWFTM2op5N88ps=; b=hF/2GcixCXLqIFk72K0lnj0excEDKCoHCGOuK84Q6+YgODzbanu8sqvXucNxtZRY6g Jmr8XKdPjomy1Sdcnfka0pG8Umbf8VHp+nIORktnMvDWK/Nbdxc9TeN7cCbUuLPloTqw yE70YXdTwzgH62OatNMHOzbCVa0NBg1LJXkmGsjVq0NBRfDeZwGXUyF92ZarJqI7dWs7 DEltiXyKX3NFeMruVjYJ4Y3OgT1Q3Bky6EkSRR9Xs2fWkJ2PgYV58XtaLPaaFaIrhQIE /H8v+FEU1irMkeXT6h5ghJuywJYfhg49+SPAZnk2e9AcyhJpBH6G2db2ouWXa4W+DoSV 0T0w== X-Gm-Message-State: ALyK8tJ7CeX+lZbIMgI4Ch27iOzJ0a3AIrF1+MZkznH9b21dv4mBAGNU2bAEKs04qoH9uvG+ X-Received: by 10.98.1.84 with SMTP id 81mr23473247pfb.155.1466445649516; Mon, 20 Jun 2016 11:00:49 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id c189sm60250353pfg.19.2016.06.20.11.00.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Jun 2016 11:00:48 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, Heiko Stuebner Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, Douglas Anderson , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/15] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Date: Mon, 20 Jun 2016 10:56:49 -0700 Message-Id: <1466445414-11974-11-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org> References: <1466445414-11974-1-git-send-email-dianders@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock frequency in order to function properly. Physically in a SoC this clock is exported from the SDHCI IP block to the PHY IP block and the PHY needs to know the speed. Let's export the SDHCI card clock using a standard device tree mechanism so that the PHY can get access to it and query the card clock frequency. Signed-off-by: Douglas Anderson Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Changes in v3: - Add collected tags Changes in v2: - Adjust commit message wording (Rob) - Add Rob Herring's Ack. Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 476604e6ce2a..3404afa9b938 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -30,6 +30,12 @@ Optional Properties: - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) used to access core corecfg registers. Offsets of registers in this syscon are determined based on the main compatible string for the device. + - clock-output-names: If specified, this will be the name of the card clock + which will be exposed by this device. Required if #clock-cells is + specified. + - #clock-cells: If specified this should be the value <0>. With this property + in place we will export a clock representing the Card Clock. This clock + is expected to be consumed by our PHY. You must also specify Example: sdhci@e0100000 { @@ -61,7 +67,9 @@ Example: arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; phys = <&emmc_phy>; phy-names = "phy_arasan"; + #clock-cells = <0>; status = "disabled"; };