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Fri, 13 May 2016 00:03:56 -0700 Received: from [172.23.64.208] (helo=xhdrdevl6.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1b178e-0006pj-5D; Fri, 13 May 2016 00:03:56 -0700 Received: by xhdrdevl6.xilinx.com (Postfix, from userid 13614) id 35EDCF2000C; Fri, 13 May 2016 12:33:55 +0530 (IST) From: Kedareswara rao Appana To: , , , , , , , , , , , , CC: , , , , "Punnaiah Choudary Kalluri" Subject: [PATCH v9 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Date: Fri, 13 May 2016 12:33:52 +0530 Message-ID: <1463123033-5443-1-git-send-email-appanad@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22318.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(9170700003)(11100500001)(36386004)(4326007)(19580405001)(50986999)(19580395003)(48376002)(2201001)(2906002)(50226002)(36756003)(50466002)(33646002)(63266004)(1220700001)(586003)(8676002)(4001430100002)(81166006)(92566002)(8936002)(6806005)(90966002)(87936001)(103686003)(47776003)(5008740100001)(229853001)(106466001)(5003940100001)(52956003)(86362001)(189998001)(45336002)(46386002)(107886002)(5001770100001)(42186005)(107986001)(921003)(2101003)(83996005)(1121003); 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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT108 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Kedareswara rao Appana Acked-by: Rob Herring --- Changs in v9: - Removed include sg runtime configuration parameter from the binding doc as suggested by Lars. Changes in v8: - Removed all the software runtime configuration parameters from the binding doc as suggested by the Lars. Changes in v7: - None. Changes in v6: - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties from the binding doc as it allow broken combinations when dma-coherent is set as suggested by Rob. - Fixed minor comments given by Rob related coding(lower case DT node name). Changes in v5: - Use dma-coherent flag for coherent transfers as suggested by rob. - Removed unnecessary properties from binding doc as suggested by Rob. Changes in v4: - None Changes in v3: - None Changes in v2: - None. .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 0000000..a784cdd --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,27 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible : Should be "xlnx,zynqmp-dma-1.0" +- reg : Memory map for gdma/adma module access. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt. +- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 +- clock-names : List of input clocks "clk_main", "clk_apb" + (see clock bindings for details) + +Optional properties: +- dma-coherent : Present if dma operations are coherent. + +Example: +++++++++ +fpd_dma_chan1: dma@fd500000 { + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xFD500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + dma-coherent; +};