From patchwork Wed Apr 27 07:05:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 615436 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qvrbR5gbpz9sD5 for ; Wed, 27 Apr 2016 17:06:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752998AbcD0HFn (ORCPT ); Wed, 27 Apr 2016 03:05:43 -0400 Received: from mail-bl2nam02on0068.outbound.protection.outlook.com ([104.47.38.68]:32096 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752437AbcD0HFk (ORCPT ); Wed, 27 Apr 2016 03:05:40 -0400 Received: from BL2NAM02FT042.eop-nam02.prod.protection.outlook.com (10.152.76.60) by BL2NAM02HT011.eop-nam02.prod.protection.outlook.com (10.152.76.150) with Microsoft SMTP Server (TLS) id 15.1.477.4; Wed, 27 Apr 2016 07:05:37 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT042.mail.protection.outlook.com (10.152.76.193) with Microsoft SMTP Server (TLS) id 15.1.477.4 via Frontend Transport; Wed, 27 Apr 2016 07:05:37 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1avJXU-0002mm-Ow; Wed, 27 Apr 2016 00:05:36 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1avJXU-00072i-LH; Wed, 27 Apr 2016 00:05:36 -0700 Received: from xsj-pvapsmtp01 (xsj-pvapsmtp01.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u3R75W3W019873; Wed, 27 Apr 2016 00:05:32 -0700 Received: from [172.23.64.207] (helo=xhd-lin64re117.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1avJXP-00071r-O4; Wed, 27 Apr 2016 00:05:31 -0700 Received: by xhd-lin64re117.xilinx.com (Postfix, from userid 13614) id E523F20D00; Wed, 27 Apr 2016 12:35:30 +0530 (IST) From: Kedareswara rao Appana To: , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Date: Wed, 27 Apr 2016 12:35:28 +0530 Message-ID: <1461740729-30715-1-git-send-email-appanad@xilinx.com> X-Mailer: git-send-email 2.1.2 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22286.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(5008740100001)(551934003)(4001450100002)(106466001)(229853001)(63266004)(50466002)(36756003)(46386002)(5003940100001)(50226002)(575784001)(6806005)(42186005)(81166005)(2201001)(45336002)(90966002)(19580395003)(4326007)(87936001)(86362001)(1096002)(19580405001)(189998001)(1220700001)(2906002)(52956003)(92566002)(5001770100001)(586003)(47776003)(50986999)(11100500001)(103686003)(48376002)(33646002)(921003)(107986001)(83996005)(1121003)(2101003); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2NAM02HT011; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 0ce48394-ace7-42a0-9828-08d36e6a55ed X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(8251501002); SRVR:BL2NAM02HT011; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(9101521072)(601004)(2401047)(13015025)(13018025)(13017025)(5005006)(13024025)(13023025)(8121501046)(3002001)(10201501046)(6055026); SRVR:BL2NAM02HT011; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT011; X-Forefront-PRVS: 0925081676 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2016 07:05:37.4094 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT011 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Kedareswara rao Appana --- Changes in v7: - None. Changes in v6: - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties from the binding doc as it allow broken combinations when dma-coherent is set as suggested by Rob. - Fixed minor comments given by Rob related coding(lower case DT node name). Changes in v5: - Use dma-coherent flag for coherent transfers as suggested by rob. - Removed unnecessary properties from binding doc as suggested by Rob. Changes in v4: - None Changes in v3: - None Changes in v2: - None. .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 0000000..f0f0b54 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,44 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible : Should be "xlnx,zynqmp-dma-1.0" +- reg : Memory map for gdma/adma module access. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt. +- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 +- clock-names : List of input clocks "clk_main", "clk_apb" + (see clock bindings for details) + +Optional properties: +- xlnx,include-sg : Indicates the controller to operate in simple or + scatter gather dma mode +- xlnx,ratectrl : Scheduling interval in terms of clock cycles for + source AXI transaction +- xlnx,overfetch : Tells whether the channel is allowed to over + fetch the data +- xlnx,src-issue : Number of AXI outstanding transactions on source side +- xlnx,src-burst-len : AXI length for data read. Support only power of + 2 byte values. +- xlnx,dst-burst-len : AXI length for data write. Support only power of + 2 byte values. +- dma-coherent : Present if dma operations are coherent. + +Example: +++++++++ +fpd_dma_chan1: dma@fd500000 { + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xFD500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + xlnx,include-sg; + xlnx,overfetch; + dma-coherent; + xlnx,ratectrl = <0>; + xlnx,src-issue = <16>; + xlnx,src-burst-len = <4>; + xlnx,dst-burst-len = <4>; +};