| Message ID | 1460365075-7316-6-git-send-email-marc.zyngier@arm.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Mon, Apr 11, 2016 at 09:57:55AM +0100, Marc Zyngier wrote: > Add a decription of the PPI partitioning support. > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > .../bindings/interrupt-controller/arm,gic-v3.txt | 34 ++++++++++++++++++++-- > 1 file changed, 32 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > index 007a5b4..4c29cda 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > @@ -11,6 +11,8 @@ Main node required properties: > - interrupt-controller : Identifies the node as an interrupt controller > - #interrupt-cells : Specifies the number of cells needed to encode an > interrupt source. Must be a single cell with a value of at least 3. > + If the system requires describing PPI affinity, then the value must > + be at least 4. You're winning for cell count... One alternative that would save adding a cell and keep it contained within would be just list the affinities in the GIC node in the form of '<PPI#> <count> <cpu phandles>': ppi-affinity = <1 2 &cpu2 &cpu3>, <5 1 &cpu4>, ... This would be harder to parse though if you have a large number of PPIs with affinities. That said, I've got no real issue with this as is. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Rob, On 12/04/16 17:29, Rob Herring wrote: > On Mon, Apr 11, 2016 at 09:57:55AM +0100, Marc Zyngier wrote: >> Add a decription of the PPI partitioning support. >> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >> --- >> .../bindings/interrupt-controller/arm,gic-v3.txt | 34 ++++++++++++++++++++-- >> 1 file changed, 32 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt >> index 007a5b4..4c29cda 100644 >> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt >> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt >> @@ -11,6 +11,8 @@ Main node required properties: >> - interrupt-controller : Identifies the node as an interrupt controller >> - #interrupt-cells : Specifies the number of cells needed to encode an >> interrupt source. Must be a single cell with a value of at least 3. >> + If the system requires describing PPI affinity, then the value must >> + be at least 4. > > You're winning for cell count... Yeah, it feels like we aim at making people's life difficult... > One alternative that would save adding a cell and keep it contained > within would be just list the affinities in the GIC node in the form of > '<PPI#> <count> <cpu phandles>': > > ppi-affinity = <1 2 &cpu2 &cpu3>, > <5 1 &cpu4>, > ... But how would that work if you have two sets of CPUs (set-1=[cpu0, cpu1]; set-2=[cpu2, cpu3]), and for the same PPI, device A is connected to set-1 and device-B is connected to set-2? You need a way to distinguish these two interrupts and so far, the only way I've found is to reference the affinity in the interrupt specifier. That being said, I'm definitely open to suggestions on how to describe this in a better way. Thanks, M.
On Tue, Apr 12, 2016 at 11:42 AM, Marc Zyngier <marc.zyngier@arm.com> wrote: > Hi Rob, > > On 12/04/16 17:29, Rob Herring wrote: >> On Mon, Apr 11, 2016 at 09:57:55AM +0100, Marc Zyngier wrote: >>> Add a decription of the PPI partitioning support. >>> >>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >>> --- >>> .../bindings/interrupt-controller/arm,gic-v3.txt | 34 ++++++++++++++++++++-- >>> 1 file changed, 32 insertions(+), 2 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt >>> index 007a5b4..4c29cda 100644 >>> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt >>> @@ -11,6 +11,8 @@ Main node required properties: >>> - interrupt-controller : Identifies the node as an interrupt controller >>> - #interrupt-cells : Specifies the number of cells needed to encode an >>> interrupt source. Must be a single cell with a value of at least 3. >>> + If the system requires describing PPI affinity, then the value must >>> + be at least 4. >> >> You're winning for cell count... > > Yeah, it feels like we aim at making people's life difficult... > >> One alternative that would save adding a cell and keep it contained >> within would be just list the affinities in the GIC node in the form of >> '<PPI#> <count> <cpu phandles>': >> >> ppi-affinity = <1 2 &cpu2 &cpu3>, >> <5 1 &cpu4>, >> ... > > But how would that work if you have two sets of CPUs (set-1=[cpu0, > cpu1]; set-2=[cpu2, cpu3]), and for the same PPI, device A is connected > to set-1 and device-B is connected to set-2? Oh right. Need to take those h/w designers out back... > You need a way to distinguish these two interrupts and so far, the only > way I've found is to reference the affinity in the interrupt specifier. > > That being said, I'm definitely open to suggestions on how to describe > this in a better way. In that case, I think it looks fine. Acked-by: Rob Herring <robh@kernel.org> Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 007a5b4..4c29cda 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -11,6 +11,8 @@ Main node required properties: - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. Must be a single cell with a value of at least 3. + If the system requires describing PPI affinity, then the value must + be at least 4. The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI interrupts. Other values are reserved for future use. @@ -24,7 +26,14 @@ Main node required properties: 1 = edge triggered 4 = level triggered - Cells 4 and beyond are reserved for future use and must have a value + The 4th cell is a phandle to a node describing a set of CPUs this + interrupt is affine to. The interrupt must be a PPI, and the node + pointed must be a subnode of the "ppi-partitions" subnode. For + interrupt types other than PPI or PPIs that are not partitionned, + this cell must be zero. See the "ppi-partitions" node description + below. + + Cells 5 and beyond are reserved for future use and must have a value of 0 if present. - reg : Specifies base physical address(s) and size of the GIC @@ -50,6 +59,11 @@ Optional Sub-nodes: +PPI affinity can be expressed as a single "ppi-partitions" node, +containing a set of sub-nodes, each with the following property: +- affinity: Should be a list of phandles to CPU nodes (as described in +Documentation/devicetree/bindings/arm/cpus.txt). + GICv3 has one or more Interrupt Translation Services (ITS) that are used to route Message Signalled Interrupts (MSI) to the CPUs. @@ -91,7 +105,7 @@ Examples: gic: interrupt-controller@2c010000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -119,4 +133,20 @@ Examples: #msi-cells = <1>; reg = <0x0 0x2c400000 0 0x200000>; }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu0 &cpu2>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu1 &cpu3>; + }; + }; + }; + + + device@0 { + reg = <0 0 0 4>; + interrupts = <1 1 4 &part0>; };
Add a decription of the PPI partitioning support. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- .../bindings/interrupt-controller/arm,gic-v3.txt | 34 ++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-)