| Message ID | 1451274454-26091-1-git-send-email-shh.xie@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
On Mon, Dec 28, 2015 at 11:47:34AM +0800, shh.xie@gmail.com wrote: > From: Shaohui Xie <Shaohui.Xie@freescale.com> > > PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs > to change corresponding serdes lane settings, so a reference is needed > for serdes lane. This patch describes properties needed for PCS PHY to > support backplane. > > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> > --- > based on: http://patchwork.ozlabs.org/patch/560936/ > > Documentation/devicetree/bindings/powerpc/fsl/fman.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > index 55c2c03..b38e727 100644 > --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > @@ -432,6 +432,16 @@ example of how to define a PHY (Internal PHY has no interrupt line). > - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. > - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, > PCS PHY addr must be '0'. > + PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs to > + change the corresponding serdes lane settings. > + > + PCS PHY node properties required for backplane: > + > + - compatible: must be "ethernet-phy-ieee802.3-c45". > + - phy-mode: string, operation mode of the PHY interface; must be "1000base-kx" > + for 1000BASE-KX, or "10gbase-kr" for 10GBASE-KR. Seems like these should be in common ethernet phy binding. > + - lane-handle: phandle, specifies a reference to a node representing a Serdes. > + - lane-range: offset and length of the register set for the serdes lane. These seem pretty FSL specific, so add vendor prefix. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> Subject: Re: [PATCH] powerpc: fsl: update fman dt binding for PCS PHY > > On Mon, Dec 28, 2015 at 11:47:34AM +0800, shh.xie@gmail.com wrote: > > From: Shaohui Xie <Shaohui.Xie@freescale.com> > > > > PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs > > to change corresponding serdes lane settings, so a reference is needed > > for serdes lane. This patch describes properties needed for PCS PHY to > > support backplane. > > > > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> > > --- > > based on: http://patchwork.ozlabs.org/patch/560936/ > > > > Documentation/devicetree/bindings/powerpc/fsl/fman.txt | 14 > > ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > > b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > > index 55c2c03..b38e727 100644 > > --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > > +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt > > @@ -432,6 +432,16 @@ example of how to define a PHY (Internal PHY has no > interrupt line). > > - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. > > - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, > > PCS PHY addr must be '0'. > > + PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this > > + needs to change the corresponding serdes lane settings. > > + > > + PCS PHY node properties required for backplane: > > + > > + - compatible: must be "ethernet-phy-ieee802.3-c45". > > + - phy-mode: string, operation mode of the PHY interface; must be "1000base- > kx" > > + for 1000BASE-KX, or "10gbase-kr" for 10GBASE-KR. > > Seems like these should be in common ethernet phy binding. [S.H] 'compatible' and 'phy-mode' are standard properties already in common Ethernet phy binding, I can update 'phy-mode' with "1000base-kx" and "10gbase-kr", how about I still list the two properties here for the requirement of PCS PHY to support backplane? > > > + - lane-handle: phandle, specifies a reference to a node representing a > Serdes. > > + - lane-range: offset and length of the register set for the serdes lane. > > These seem pretty FSL specific, so add vendor prefix. [S.H] OK. will add fsl prefix. Thank you for reviewing the patch! Shaohui -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Dec 29, 2015 at 9:41 PM, Shaohui Xie <shaohui.xie@nxp.com> wrote: >> Subject: Re: [PATCH] powerpc: fsl: update fman dt binding for PCS PHY >> >> On Mon, Dec 28, 2015 at 11:47:34AM +0800, shh.xie@gmail.com wrote: >> > From: Shaohui Xie <Shaohui.Xie@freescale.com> >> > >> > PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs >> > to change corresponding serdes lane settings, so a reference is needed >> > for serdes lane. This patch describes properties needed for PCS PHY to >> > support backplane. >> > >> > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> >> > --- >> > based on: http://patchwork.ozlabs.org/patch/560936/ >> > >> > Documentation/devicetree/bindings/powerpc/fsl/fman.txt | 14 >> > ++++++++++++++ >> > 1 file changed, 14 insertions(+) >> > >> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt >> > b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt >> > index 55c2c03..b38e727 100644 >> > --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt >> > +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt >> > @@ -432,6 +432,16 @@ example of how to define a PHY (Internal PHY has no >> interrupt line). >> > - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. >> > - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, >> > PCS PHY addr must be '0'. >> > + PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this >> > + needs to change the corresponding serdes lane settings. >> > + >> > + PCS PHY node properties required for backplane: >> > + >> > + - compatible: must be "ethernet-phy-ieee802.3-c45". >> > + - phy-mode: string, operation mode of the PHY interface; must be "1000base- >> kx" >> > + for 1000BASE-KX, or "10gbase-kr" for 10GBASE-KR. >> >> Seems like these should be in common ethernet phy binding. > [S.H] 'compatible' and 'phy-mode' are standard properties already in common Ethernet > phy binding, I can update 'phy-mode' with "1000base-kx" and "10gbase-kr", how > about I still list the two properties here for the requirement of PCS PHY to support > backplane? Yes. The common binding should list all possible values and this binding should list allowed values. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> > [S.H] 'compatible' and 'phy-mode' are standard properties already in > > common Ethernet phy binding, I can update 'phy-mode' with > > "1000base-kx" and "10gbase-kr", how about I still list the two > > properties here for the requirement of PCS PHY to support backplane? > > Yes. The common binding should list all possible values and this binding should > list allowed values. Got it. Thank you! Shaohui
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt index 55c2c03..b38e727 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt @@ -432,6 +432,16 @@ example of how to define a PHY (Internal PHY has no interrupt line). - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, PCS PHY addr must be '0'. + PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs to + change the corresponding serdes lane settings. + + PCS PHY node properties required for backplane: + + - compatible: must be "ethernet-phy-ieee802.3-c45". + - phy-mode: string, operation mode of the PHY interface; must be "1000base-kx" + for 1000BASE-KX, or "10gbase-kr" for 10GBASE-KR. + - lane-handle: phandle, specifies a reference to a node representing a Serdes. + - lane-range: offset and length of the register set for the serdes lane. EXAMPLE @@ -464,7 +474,11 @@ mdio@f1000 { fsl,fman-internal-mdio; pcsphy6: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "10gbase-kr"; reg = <0x0>; + lane-handle = <&serdes>; + lane-range = <0x18c0 0x40>; }; };