From patchwork Wed Dec 16 10:10:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 557378 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 90E7A1402C4 for ; Wed, 16 Dec 2015 21:11:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965671AbbLPKKk (ORCPT ); Wed, 16 Dec 2015 05:10:40 -0500 Received: from mail-pf0-f180.google.com ([209.85.192.180]:34126 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965656AbbLPKKi (ORCPT ); Wed, 16 Dec 2015 05:10:38 -0500 Received: by mail-pf0-f180.google.com with SMTP id 68so9935240pfc.1; Wed, 16 Dec 2015 02:10:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=618+4QK1cZAjSh3JUL/O+iRVCaAAy8DExnoDcMqb+Vs=; b=IcgqCjVnOpirw+CBRxSXyWPDCl0KVHMyTz0g3lyeAQOi5gehKcGPdgfsWlrNCUTnm+ fuTBDCe4OU4q3JhwCJKohD5zeSxte5RPq8R/tglbxWLcG9/TxwP6v8Ynv4S07OLqeHIo HLb9U3uZCVyjKj547yfshUwXsZ1TLQ8R3Cf5Hhsp6d/E4f0ifn7ZgZxNYTAg7qT3GAqh Fw6DEzyA+xkmyJ2CbKywa70HNvEHXd8L+Ei3Uh8SrCf45KBTPOpGgmsBONSeJm3gb/ar zu8+Pfpa6Scv0dCsJ5RaZ3t9YF+QfpH9iHixITLfNHH6nZM1bIUAxnWW+dax/kkxQBU5 Isbg== X-Received: by 10.98.16.204 with SMTP id 73mr4110381pfq.136.1450260638315; Wed, 16 Dec 2015 02:10:38 -0800 (PST) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id u14sm3688263pfi.58.2015.12.16.02.10.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 16 Dec 2015 02:10:37 -0800 (PST) From: Chris Zhong To: heiko@sntech.de, linux-rockchip@lists.infradead.org, mark.yao@rock-chips.com, treding@nvidia.com Cc: Chris Zhong , devicetree@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Ian Campbell , Rob Herring , Pawel Moll , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 3/6] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver Date: Wed, 16 Dec 2015 18:10:13 +0800 Message-Id: <1450260616-21160-4-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1450260616-21160-1-git-send-email-zyw@rock-chips.com> References: <1450260616-21160-1-git-send-email-zyw@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v6: - update the document, since the bridge device has been deleted. Changes in v5: None Changes in v4: None Changes in v3: - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt new file mode 100644 index 0000000..1753f0c --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -0,0 +1,60 @@ +Rockchip specific extensions to the Synopsys Designware MIPI DSI +================================ + +Required properties: +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. +- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". +- reg: Represent the physical address range of the controller. +- interrupts: Represent the controller's interrupt to the CPU(s). +- clocks, clock-names: Phandles to the controller's pll reference + clock(ref) and APB clock(pclk), as described in [1]. +- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. +- ports: contain a port node with endpoint definitions as defined in [2]. + For vopb,set the reg = <0> and set the reg = <1> for vopl. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + mipi_dsi: mipi@ff960000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0xff960000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; + rockchip,grf = <&grf>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + + panel { + compatible ="boe,tv080wum-nl0"; + reg = <0>; + + enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + backlight = <&backlight>; + status = "okay"; + }; + };