| Message ID | 1447616777-24660-1-git-send-email-hdegoede@redhat.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote: > From: Reinder de Haan <patchesrdh@mveas.com> > > The H3 has a usb-phy clk register which is similar to that of earlier > SoCs, but with support for a larger number of phys. So we can simply add > a new set of clk-data and a new compatible and be done with it. > > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Chen-Yu Tsai <wens@csie.org> > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index d303dec..23e7bce 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -70,6 +70,7 @@ Required properties: > "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 > "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 > "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 > + "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 > "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 > > diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c > index 1a72cd6..67b8e38 100644 > --- a/drivers/clk/sunxi/clk-usb.c > +++ b/drivers/clk/sunxi/clk-usb.c > @@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node) > sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock); > } > CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup); > + > +static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = { > + .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) | > + BIT(11) | BIT(10) | BIT(9) | BIT(8), > + .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), > +}; > + > +static void __init sun8i_h3_usb_setup(struct device_node *node) > +{ > + sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock); > +} > +CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup); > -- > 2.5.0 > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote: > From: Reinder de Haan <patchesrdh@mveas.com> > > Add a node describing the usb-clks found on the H3. > > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Chen-Yu Tsai <wens@csie.org> (Also updated Mike's email in my reply.) > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > index c18b5f7..22ff593 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -266,6 +266,18 @@ > "mmc2_sample"; > }; > > + usb_clk: clk@01c200cc { > + #clock-cells = <1>; > + #reset-cells = <1>; > + compatible = "allwinner,sun8i-h3-usb-clk"; > + reg = <0x01c200cc 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "usb_phy0", "usb_phy1", > + "usb_phy2", "usb_phy3", > + "usb_ohci0", "usb_ohci1", > + "usb_ohci2", "usb_ohci3"; > + }; > + > mbus_clk: clk@01c2015c { > #clock-cells = <0>; > compatible = "allwinner,sun8i-a23-mbus-clk"; > -- > 2.5.0 > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote: > From: Reinder de Haan <patchesrdh@mveas.com> > > Enable the 3 pairs of USB host controllers used on the Orange Pi Plus. > > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts > index e67df59..e05a409 100644 > --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts > +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts > @@ -60,6 +60,18 @@ > }; > }; > > +&ehci1 { > + status = "okay"; > +}; > + > +&ehci2 { > + status = "okay"; > +}; > + > +&ehci3 { > + status = "okay"; > +}; > + > &mmc0 { > pinctrl-names = "default"; > pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; > @@ -70,8 +82,24 @@ > status = "okay"; > }; > > +&ohci1 { > + status = "okay"; > +}; This controller is connected to a FE1.1s USB 2.0 hub, giving us the four usable external USB ports. We shouldn't need to enable OHCI. > + > +&ohci2 { > + status = "okay"; > +}; According to the schematics, this port is never used. Please remove. > +&ohci3 { > + status = "okay"; > +}; This is connected to the GL830 USB-SATA bridge. Again, OHCI isn't needed. > + > &uart0 { > pinctrl-names = "default"; > pinctrl-0 = <&uart0_pins_a>; > status = "okay"; > }; > + > +&usbphy { > + status = "okay"; And what about power supplies / regulators? Regards ChenYu > +}; > -- > 2.5.0 > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On 16-11-15 04:00, Chen-Yu Tsai wrote: > Hi, > > On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote: >> From: Reinder de Haan <patchesrdh@mveas.com> >> >> Enable the 3 pairs of USB host controllers used on the Orange Pi Plus. >> >> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> >> Signed-off-by: Hans de Goede <hdegoede@redhat.com> >> --- >> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> index e67df59..e05a409 100644 >> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> @@ -60,6 +60,18 @@ >> }; >> }; >> >> +&ehci1 { >> + status = "okay"; >> +}; >> + >> +&ehci2 { >> + status = "okay"; >> +}; >> + >> +&ehci3 { >> + status = "okay"; >> +}; >> + >> &mmc0 { >> pinctrl-names = "default"; >> pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; >> @@ -70,8 +82,24 @@ >> status = "okay"; >> }; >> >> +&ohci1 { >> + status = "okay"; >> +}; > > This controller is connected to a FE1.1s USB 2.0 hub, giving us the > four usable external USB ports. We shouldn't need to enable OHCI. Right, my bad, I actually tested this on an orangepi pc, for which we need to create a new dts of course, the orangepi pc does have all 3 controllers routed directly to the outside. >> + >> +&ohci2 { >> + status = "okay"; >> +}; > > According to the schematics, this port is never used. Please remove. The same goes for ehci2 then, otherwise ack. > >> +&ohci3 { >> + status = "okay"; >> +}; > > This is connected to the GL830 USB-SATA bridge. Again, OHCI isn't > needed. My bad again. >> + >> &uart0 { >> pinctrl-names = "default"; >> pinctrl-0 = <&uart0_pins_a>; >> status = "okay"; >> }; >> + >> +&usbphy { >> + status = "okay"; > > And what about power supplies / regulators? On the orangepi pc none are needed. Jens can you test this series (or my sunxi-wip kernel branch) on your orangepi plus ? and send an updated version of this patch with the necessary changes? I do not actually have an orangepi plus. Regards, Hans -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sun, Nov 15, 2015 at 08:46:13PM +0100, Hans de Goede wrote: > From: Reinder de Haan <patchesrdh@mveas.com> > > The H3 has a usb-phy clk register which is similar to that of earlier > SoCs, but with support for a larger number of phys. So we can simply add > a new set of clk-data and a new compatible and be done with it. > > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Rob Herring <robh@kernel.org> > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index d303dec..23e7bce 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -70,6 +70,7 @@ Required properties: > "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 > "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 > "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 > + "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 > "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 > > diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c > index 1a72cd6..67b8e38 100644 > --- a/drivers/clk/sunxi/clk-usb.c > +++ b/drivers/clk/sunxi/clk-usb.c > @@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node) > sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock); > } > CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup); > + > +static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = { > + .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) | > + BIT(11) | BIT(10) | BIT(9) | BIT(8), > + .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), > +}; > + > +static void __init sun8i_h3_usb_setup(struct device_node *node) > +{ > + sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock); > +} > +CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup); > -- > 2.5.0 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Nov 16, 2015 at 10:36:02AM +0800, Chen-Yu Tsai wrote: > On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote: > > From: Reinder de Haan <patchesrdh@mveas.com> > > > > The H3 has a usb-phy clk register which is similar to that of earlier > > SoCs, but with support for a larger number of phys. So we can simply add > > a new set of clk-data and a new compatible and be done with it. > > > > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > > Acked-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks! Maxime
Hi, On 17-11-15 17:12, Jens Kuske wrote: > Enable the 2 USB host controllers used on the Orange Pi Plus > and add the necessary regulators. > > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > Signed-off-by: Jens Kuske <jenskuske@gmail.com> > --- > > Hi Hans, > > with these regulators USB works on the Orange Pi Plus too. > I don't know if adding the regulators in the dts is okay, since most > regulators are defined in the sunxi-common-regulators.dtsi, but > we use different pins. Thanks, I've added this to my sunxi-wip branch for now. Regards, Hans p.s. Any progress on getting the "core" H3 kernel support upstream ? Given Arnd's remarks about how we should not hard-code the indices in the clk driver + the very KISS nature of the change to 1 parent-clk per gate setup I still believe that that one is best. Maxime ? Chen-Yu ? It would be really good to be able to move forward with this, how do you want to proceed ? > > Jens > > > arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 ++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts > index e67df59..1cb6c66 100644 > --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts > +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts > @@ -58,6 +58,35 @@ > chosen { > stdout-path = "serial0:115200n8"; > }; > + > + reg_usb3_vbus: usb3-vbus { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&usb3_vbus_pin_a>; > + regulator-name = "usb3-vbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-boot-on; > + enable-active-high; > + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; > + }; > +}; > + > +&ehci1 { > + status = "okay"; > +}; > + > +&ehci3 { > + status = "okay"; > +}; > + > +&pio { > + usb3_vbus_pin_a: usb3_vbus_pin@0 { > + allwinner,pins = "PG11"; > + allwinner,function = "gpio_out"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > }; > > &mmc0 { > @@ -70,8 +99,23 @@ > status = "okay"; > }; > > +®_usb1_vbus { > + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; > + > &uart0 { > pinctrl-names = "default"; > pinctrl-0 = <&uart0_pins_a>; > status = "okay"; > }; > + > +&usb1_vbus_pin_a { > + allwinner,pins = "PG13"; > +}; > + > +&usbphy { > + usb1_vbus-supply = <®_usb1_vbus>; > + usb3_vbus-supply = <®_usb3_vbus>; > + status = "okay"; > +}; > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Fri, Nov 20, 2015 at 03:38:47PM +0100, Hans de Goede wrote: > Hi, > > On 17-11-15 17:12, Jens Kuske wrote: > >Enable the 2 USB host controllers used on the Orange Pi Plus > >and add the necessary regulators. > > > >Signed-off-by: Reinder de Haan <patchesrdh@mveas.com> > >Signed-off-by: Hans de Goede <hdegoede@redhat.com> > >Signed-off-by: Jens Kuske <jenskuske@gmail.com> > >--- > > > >Hi Hans, > > > >with these regulators USB works on the Orange Pi Plus too. > >I don't know if adding the regulators in the dts is okay, since most > >regulators are defined in the sunxi-common-regulators.dtsi, but > >we use different pins. > > Thanks, I've added this to my sunxi-wip branch for now. > > Regards, > > Hans > > p.s. > > Any progress on getting the "core" H3 kernel support upstream ? > > Given Arnd's remarks about how we should not hard-code the > indices in the clk driver + the very KISS nature of the > change to 1 parent-clk per gate setup I still believe > that that one is best. > > Maxime ? Chen-Yu ? It would be really good to be able to > move forward with this, how do you want to proceed ? Yeah, sorry, Chen-Yu and I were busy because of $LIFE the past weeks, we're getting back to speed. Maxime
Hi, On 23-11-15 23:20, Troy Dack wrote: > > > On Wednesday, 18 November 2015 03:12:11 UTC+11, Jens Kuske wrote: >> >> Enable the 2 USB host controllers used on the Orange Pi Plus >> and add the necessary regulators. >> >> Signed-off-by: Reinder de Haan <patch...@mveas.com <javascript:>> >> Signed-off-by: Hans de Goede <hdeg...@redhat.com <javascript:>> >> Signed-off-by: Jens Kuske <jens...@gmail.com <javascript:>> >> --- >> >> Hi Hans, >> >> with these regulators USB works on the Orange Pi Plus too. >> I don't know if adding the regulators in the dts is okay, since most >> regulators are defined in the sunxi-common-regulators.dtsi, but >> we use different pins. >> >> Jens >> >> >> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 >> ++++++++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> index e67df59..1cb6c66 100644 >> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts >> @@ -58,6 +58,35 @@ >> chosen { >> stdout-path = "serial0:115200n8"; >> }; >> + >> + reg_usb3_vbus: usb3-vbus { >> + compatible = "regulator-fixed"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&usb3_vbus_pin_a>; >> + regulator-name = "usb3-vbus"; >> + regulator-min-microvolt = <5000000>; >> + regulator-max-microvolt = <5000000>; >> + regulator-boot-on; >> + enable-active-high; >> + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; >> + }; >> +}; >> + >> +&ehci1 { >> + status = "okay"; >> +}; >> + >> +&ehci3 { >> + status = "okay"; >> +}; >> + >> +&pio { >> + usb3_vbus_pin_a: usb3_vbus_pin@0 { >> + allwinner,pins = "PG11"; >> + allwinner,function = "gpio_out"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> }; >> >> &mmc0 { >> @@ -70,8 +99,23 @@ >> status = "okay"; >> }; >> >> +®_usb1_vbus { >> + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; >> + status = "okay"; >> +}; >> + >> &uart0 { >> pinctrl-names = "default"; >> pinctrl-0 = <&uart0_pins_a>; >> status = "okay"; >> }; >> + >> +&usb1_vbus_pin_a { >> + allwinner,pins = "PG13"; >> +}; >> + >> +&usbphy { >> + usb1_vbus-supply = <®_usb1_vbus>; >> + usb3_vbus-supply = <®_usb3_vbus>; >> + status = "okay"; >> +}; >> > > I've been trying to test these patches by using Hans' github sunxi-wip > branches of the kernel and U-Boot. > > U-Boot at commit 7e17fd2 "suxni: Add support for Orangepi Plus and Orangepi > PC boards" > Kernel at commit cb45b8 "ARM: dts: sun8i-h3-orangepi-plus: Enable USB host > controllers" > > Both have been built using the default defconfig for an OrangePi Plus > > U-Boot starts and successfully boots the kernel, but the kernel does not > appear to boot fully and hangs at: > > [ 0.861175] cpu cpu0: failed to get cpu0 clock: -2 > [ 0.865973] cpufreq-dt: probe of cpufreq-dt failed with error -2 > [ 0.872017] Registering SWP/SWPB emulation handler > > Full boot log: http://pastebin.com/VGkEix9p > > Building the kernel (or just using a dab) with the dts from commit 0a8c01 > "ARM: dts: sun8i: Add Orange Pi Plus support" results in the kernel booting > fully to a login prompt. Of course without enabled/working USB. > > There is a fair chance I've done something wrong that is causing this. Any > advice on how to get a bootable kernel? Weird, are you sure you updated both the dtb and [u|z]image at the same time ? I'm using this kernel config: https://fedorapeople.org/~jwrdegoede/kernel-driver-programming/kernel-config With that everything you need is builtin, no need to build modules. Regards, Hans -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index d303dec..23e7bce 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -70,6 +70,7 @@ Required properties: "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 + "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c index 1a72cd6..67b8e38 100644 --- a/drivers/clk/sunxi/clk-usb.c +++ b/drivers/clk/sunxi/clk-usb.c @@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node) sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock); } CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup); + +static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = { + .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) | + BIT(11) | BIT(10) | BIT(9) | BIT(8), + .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), +}; + +static void __init sun8i_h3_usb_setup(struct device_node *node) +{ + sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock); +} +CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);