From patchwork Tue Oct 6 19:01:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 526898 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 22E3F140D71 for ; Wed, 7 Oct 2015 06:02:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752820AbbJFTB5 (ORCPT ); Tue, 6 Oct 2015 15:01:57 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:52910 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753029AbbJFTBy (ORCPT ); Tue, 6 Oct 2015 15:01:54 -0400 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 8F2526223; Tue, 6 Oct 2015 13:01:53 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 41147E40CD; Tue, 6 Oct 2015 13:01:50 -0600 (MDT) From: Stephen Warren To: Thierry Reding , Alexandre Courbot , Andrew Bresticker Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, Stephen Warren , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Mathias Nyman , Greg Kroah-Hartman Subject: [PATCH V9] dt: add NVIDIA Tegra XUSB controller binding Date: Tue, 6 Oct 2015 13:01:49 -0600 Message-Id: <1444158109-1590-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.98.6 at avon.wwwdotorg.org X-Virus-Status: Clean Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Stephen Warren Add device-tree binding documentation for the XUSB (xHCI) controller present on Tegra124 and later SoCs. Signed-off-by: Andrew Bresticker [swarren, combined separate MFD, mailbox, XHCI bindings into one node] Signed-off-by: Stephen Warren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Mathias Nyman Cc: Greg Kroah-Hartman --- Changes from v8: - Combined the separate MFD, mailbox, and XHCI bindings into one; there is a single HW module, and so there should be a single DT node to represent it. Any Linux-internal driver structure should not influence the binding structure. This included squashing the various reg and interrupt resources that were previously in the separate modules into one list. - Used lists to document the compatible, reg, and interrupts properties. - Renamed the primary binding from xhci to xusb to reflect the name of the overall module. Changes from v7: - Added back non-shared reg/interrupts properties. Changes from v6: - Removed XUSB_DEV related clocks/resets. They will be consumed by a separate driver and binding. - Removed reg/interrupts properties. No changes from v5. Changes from v4: - Updated regulator names, as suggested by Thierry. No changes from v3. Changes from v2: - Added mbox-names property. Changes from v1: - Updated to use common mailbox bindings. - Added remaining XUSB-related clocks and resets. - Updated list of power supplies to be more accurate wrt to the hardware. --- .../bindings/usb/nvidia,tegra124-xusb.txt | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt new file mode 100644 index 000000000000..f8de8d49602e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -0,0 +1,96 @@ +NVIDIA Tegra XUSB (XHCI) controller +=================================== + +The Tegra XUSB controller supports both USB2 and USB3 interfaces exposed +by the Tegra XUSB pad controller. + +Required properties: +-------------------- + - compatible: Valid options are: + - Tegra124: "nvidia,tegra124-xusb". + - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb". + - reg: Must contain the following entries, in the following order: + - The xHCI host registers. + - The IPFS registers. + - The FPCI registers. + - interrupts: Must contain the following entries, in the following order: + - The xHCI host interrupt + - The XUSB mailbox interrupt. + - clocks: Must contain an entry for each entry in clock-names. + See ../clock/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - xusb_host + - xusb_host_src + - xusb_falcon_src + - xusb_ss + - xusb_ss_src + - xusb_ss_div2 + - xusb_hs_src + - xusb_fs_src + - pll_u_480m + - clk_m + - pll_e + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - xusb_host + - xusb_ss + - xusb_src + Note that xusb_src is the shared reset for xusb_{ss,hs,fs,falcon,host}_src. + - avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05V. + - dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05V. + - avdd-usb-supply: USB controller power supply. Must supply 3.3V. + - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8V. + - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05V. + - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05V. + - hvdd-usb-ss-supply: High-voltage PCIe/USB3 power supply. Must supply 3.3V. + - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3V. + +Optional properties: +-------------------- + - phys: Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + - phy-names: Should include an entry for each PHY used by the controller. + Names must be of the form "-" where is one of "utmi", + "hsic", or "usb3" and is a 0-based index. On Tegra124, there may + be up to 3 UTMI, 2 HSIC, and 2 USB3 PHYs. + +Example: +-------- + usb-host@0,70090000 { + compatible = "nvidia,tegra124-xusb"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70099000 0x0 0x1000>, + <0x0 0x70098000 0x0 0x1000>; + interrupts = , + ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", + "xusb_ss", "xusb_ss_div2", "xusb_ss_src", + "xusb_hs_src", "xusb_fs_src", "pll_u_480m", + "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; + reset-names = "xusb_host", "xusb_ss", "xusb_src"; + phys = <&padctl TEGRA_XUSB_PADCTL_UTMI_P1>, /* mini-PCIe USB */ + <&padctl TEGRA_XUSB_PADCTL_UTMI_P2>, /* USB A */ + <&padctl TEGRA_XUSB_PADCTL_USB3_P0>; /* USB A */ + phy-names = "utmi-1", "utmi-2", "usb3-0"; + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-usb-ss-pll-supply = <&vdd_1v05_run>; + hvdd-usb-ss-supply = <&vdd_3v3_lp0>; + hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; + };