diff mbox

[1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation

Message ID 1442389379-9298-2-git-send-email-gabriel.fernandez@linaro.org
State Not Applicable, archived
Headers show

Commit Message

Gabriel Fernandez Sept. 16, 2015, 7:42 a.m. UTC
replace "sst,plls-c32-cx_x" by "st,plls-c32-cx_x"

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Rob Herring (Arm) Sept. 21, 2015, 3:04 p.m. UTC | #1
On 09/16/2015 02:42 AM, Gabriel Fernandez wrote:
> replace "sst,plls-c32-cx_x" by "st,plls-c32-cx_x"

Ironically, the subject has a typo...

Acked-by: Rob Herring <robh@kernel.org>

> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
>  Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> index d8b168e..e2c6db0 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> @@ -21,8 +21,8 @@ Required properties:
>  	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"
>  	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"
>  	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"
> -	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"
> -	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"
> +	"st,plls-c32-cx_0",		"st,clkgen-plls-c32"
> +	"st,plls-c32-cx_1",		"st,clkgen-plls-c32"
>  
>  	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"
>  	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"
> 

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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index d8b168e..e2c6db0 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@  Required properties:
 	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"
 	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"
 	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"
-	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"
-	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"
+	"st,plls-c32-cx_0",		"st,clkgen-plls-c32"
+	"st,plls-c32-cx_1",		"st,clkgen-plls-c32"
 
 	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"
 	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"