From patchwork Thu Jul 30 13:06:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 502149 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2F5EE1401AD for ; Thu, 30 Jul 2015 23:07:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752659AbbG3NHH (ORCPT ); Thu, 30 Jul 2015 09:07:07 -0400 Received: from mga02.intel.com ([134.134.136.20]:9515 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752472AbbG3NHE (ORCPT ); Thu, 30 Jul 2015 09:07:04 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 30 Jul 2015 06:06:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,577,1432623600"; d="scan'208";a="738792561" Received: from smile.fi.intel.com (HELO smile) ([10.237.72.90]) by orsmga001.jf.intel.com with ESMTP; 30 Jul 2015 06:06:33 -0700 Received: from andy by smile with local (Exim 4.86) (envelope-from ) id 1ZKnXc-0003Qy-1p; Thu, 30 Jul 2015 16:06:32 +0300 From: Andy Shevchenko To: Rob Herring , Nicolas Ferre , Greg Kroah-Hartman , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, Cyrille Pitchen , Hans-Christian Egtvedt , alexandre.belloni@free-electrons.com Cc: Andy Shevchenko Subject: [PATCH v1 1/2] dt: atmel-usart: document new I/O data register width property Date: Thu, 30 Jul 2015 16:06:30 +0300 Message-Id: <1438261591-13130-1-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.5.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This change documents a new property for the Atmel serial device, allowing an implementer to specify either four bytes or one byte access to the controller data register. This supports a change that unbreaks this driver on ATNGW100 board. Signed-off-by: Andy Shevchenko --- Documentation/devicetree/bindings/serial/atmel-usart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt index e6e6142..a8c290a7 100644 --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt +++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt @@ -6,6 +6,8 @@ Required properties: additional mode or an USART new feature. For the dbgu UART, use "atmel,-dbgu", "atmel,-usart" - reg: Should contain registers location and length +- reg-io-width: The I/O register width (in bytes) implemented by + this device. Supported values are 1 or 4 (the default). - interrupts: Should contain interrupt - clock-names: tuple listing input clock names. Required elements: "usart"