From patchwork Mon May 4 17:36:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 467768 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3A3A81402D5 for ; Tue, 5 May 2015 03:39:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751677AbbEDRiD (ORCPT ); Mon, 4 May 2015 13:38:03 -0400 Received: from mail-ob0-f201.google.com ([209.85.214.201]:34152 "EHLO mail-ob0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752141AbbEDRgy (ORCPT ); Mon, 4 May 2015 13:36:54 -0400 Received: by obbgq1 with SMTP id gq1so10270497obb.1 for ; Mon, 04 May 2015 10:36:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mNKGN5rtoLhgbpc+RcbROCRPMW6jL270TcX5jxuLyOs=; b=FRNVZp8OefKx82F8bVFiIJ5Ql4Rj7Nqo5wpg5d57eqmErjLoxVRbm+t8/zqEPYP/09 B6KmneTfztz8+I7nge+W8Mafomm6z9gFjRG6a6aD5jPAPmev5GN7ff6EHqI8ZWDsYl67 3ty7vfdO1KTbwIBEpraHTVd+9IWx3ckLhdz5AAQPJ6Z725SkeT1D2Hp0vaK8b5dK6PDR LDXry/9+BbPOXD2BuYX/0rDXbfnx5+zbXITjzaK7IH2+v9D5EjmHu+WnFuUWjci6K17q Cj3tuYXT6g0QwIc49KSc4aHC6ap+LZZvp8qvFOokT20yrkfpE4Jy4F/b0CH04CJxxXES kHiw== X-Gm-Message-State: ALoCoQmUE7rqK6vUxXK1I3RnDcE2Gu/wJW4rruNx/hsR0I/68VpmoLBei2/FDZGLFQNPRSva502e X-Received: by 10.43.130.198 with SMTP id hn6mr47780014icc.26.1430761013763; Mon, 04 May 2015 10:36:53 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id x25si730002yha.2.2015.05.04.10.36.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 May 2015 10:36:53 -0700 (PDT) Received: from abrestic.mtv.corp.google.com ([172.22.65.70]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id JmoY0soO.2; Mon, 04 May 2015 10:36:53 -0700 Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 56AB5A4919; Mon, 4 May 2015 10:36:52 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , Alexandre Courbot Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker , Jon Hunter , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Mathias Nyman , Greg Kroah-Hartman Subject: [PATCH v8 8/9] usb: Add NVIDIA Tegra xHCI controller binding Date: Mon, 4 May 2015 10:36:41 -0700 Message-Id: <1430761002-9327-9-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1430761002-9327-1-git-send-email-abrestic@chromium.org> References: <1430761002-9327-1-git-send-email-abrestic@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device-tree binding documentation for the xHCI controller present on Tegra124 and later SoCs. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Mathias Nyman Cc: Greg Kroah-Hartman --- Changes from v7: - Added back non-shared reg/interrupts properties. Changes from v6: - Removed XUSB_DEV related clocks/resets. They will be consumed by a separate driver and binding. - Removed reg/interrupts properties. No changes from v5. Changes from v4: - Updated regulator names, as suggested by Thierry. No changes from v3. Changes from v2: - Added mbox-names property. Changes from v1: - Updated to use common mailbox bindings. - Added remaining XUSB-related clocks and resets. - Updated list of power supplies to be more accurate wrt to the hardware. --- .../bindings/usb/nvidia,tegra124-xhci.txt | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt new file mode 100644 index 0000000..54d21c7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt @@ -0,0 +1,96 @@ +NVIDIA Tegra xHCI controller +============================ + +The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed +by the Tegra XUSB pad controller. + +Required properties: +-------------------- + - compatible: For Tegra124, must contain "nvidia,tegra124-xhci". + Otherwise, must contain '"nvidia,-xhci", "nvidia,tegra124-xhci"' + where is tegra132. + - reg: Must contain the base and length of the xHCI host registers and XUSB + IPFS registers. + - interrupts: Must contain the xHCI host interrupt. + - clocks: Must contain an entry for each entry in clock-names. + See ../clock/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - xusb_host + - xusb_host_src + - xusb_falcon_src + - xusb_ss + - xusb_ss_src + - xusb_ss_div2 + - xusb_hs_src + - xusb_fs_src + - pll_u_480m + - clk_m + - pll_e + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - xusb_host + - xusb_ss + - xusb_src + Note that xusb_src is the shared reset for xusb_{ss,hs,fs,falcon,host}_src. + - mboxes: Must contain an entry for the XUSB mailbox channel. + See ../mailbox/mailbox.txt for details. + - mbox-names: Must include the following entries: + - xusb + - avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05V. + - dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05V. + - avdd-usb-supply: USB controller power supply. Must supply 3.3V. + - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8V. + - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05V. + - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05V. + - hvdd-usb-ss-supply: High-voltage PCIe/USB3 power supply. Must supply 3.3V. + - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3V. + +Optional properties: +-------------------- + - phys: Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + - phy-names: Should include an entry for each PHY used by the controller. + Names must be of the form "-" where is one of "utmi", + "hsic", or "usb3" and is a 0-based index. On Tegra124, there may + be up to 3 UTMI, 2 HSIC, and 2 USB3 PHYs. + +Example: +-------- + usb-host@0,70090000 { + compatible = "nvidia,tegra124-xhci"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70099000 0x0 0x1000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", + "xusb_ss", "xusb_ss_div2", "xusb_ss_src", + "xusb_hs_src", "xusb_fs_src", "pll_u_480m", + "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; + reset-names = "xusb_host", "xusb_ss", "xusb_src"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; + phys = <&padctl TEGRA_XUSB_PADCTL_UTMI_P1>, /* mini-PCIe USB */ + <&padctl TEGRA_XUSB_PADCTL_UTMI_P2>, /* USB A */ + <&padctl TEGRA_XUSB_PADCTL_USB3_P0>; /* USB A */ + phy-names = "utmi-1", "utmi-2", "usb3-0"; + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-usb-ss-pll-supply = <&vdd_1v05_run>; + hvdd-usb-ss-supply = <&vdd_3v3_lp0>; + hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; + };