From patchwork Sun Apr 19 12:58:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alban X-Patchwork-Id: 462543 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3444C140134 for ; Sun, 19 Apr 2015 22:59:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753134AbbDSM7u (ORCPT ); Sun, 19 Apr 2015 08:59:50 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:40269 "EHLO smtp1-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753156AbbDSM7u (ORCPT ); Sun, 19 Apr 2015 08:59:50 -0400 Received: from localhost.localdomain (unknown [85.177.79.58]) (Authenticated sender: albeu) by smtp1-g21.free.fr (Postfix) with ESMTPA id 44A46940091; Sun, 19 Apr 2015 14:57:19 +0200 (CEST) From: Alban Bedel To: linux-mips@linux-mips.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Jason Cooper , Ralf Baechle , Alban Bedel , Andrew Bresticker , Qais Yousef , Gabor Juhos , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/12] devicetree: Add bindings for the ATH79 MISC interrupt controllers Date: Sun, 19 Apr 2015 14:58:01 +0200 Message-Id: <1429448288-20742-6-git-send-email-albeu@free.fr> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1429448288-20742-1-git-send-email-albeu@free.fr> References: <1429448288-20742-1-git-send-email-albeu@free.fr> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Alban Bedel --- v2: * Fixed the node names to respect ePAPR --- .../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt new file mode 100644 index 0000000..391717a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt @@ -0,0 +1,30 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller + +The MISC interrupt controller is a secondary controller for lower priority +interrupt. + +Required Properties: +- compatible: has to be "qca,-cpu-intc", "qca,ar7100-misc-intc" + as fallback +- reg: Base address and size of the controllers memory area +- interrupt-parent: phandle of the parent interrupt controller. +- interrupts: Interrupt specifier for the controllers interrupt. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 1 + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Example: + + interrupt-controller@18060010 { + compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + };