From patchwork Thu Mar 12 14:47:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 449509 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 115741400DE for ; Fri, 13 Mar 2015 02:01:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=Oirqv9Gb; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754868AbbCLOuJ (ORCPT ); Thu, 12 Mar 2015 10:50:09 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:33091 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754370AbbCLOuE (ORCPT ); Thu, 12 Mar 2015 10:50:04 -0400 Received: by widfb4 with SMTP id fb4so4617845wid.0; Thu, 12 Mar 2015 07:50:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8wkyfRKW26Bg2eDnv1Sa9zV/q7xF+puMj6NdNP6vtfM=; b=Oirqv9Gb85hDnt7eSjkv9tw3lmiCzD8GvAD797rtVR4mkpfR1DT6jmmxs03ZobLCVf eVx5iWj+mTLs0IX8IxpYBDiMTywfLOgcMnBw6EoHLmfkskbpBl0yd1q+LBIQb1aCtrur qa4ljAIvTUpJF3rpXGo4fzkX5vnT1pBI7jW6RZIqCiJTvO9DAPSopmMyKN/A8U6IXPV5 3MZ6FPIhqSgPEmROYAkHv7Gp2TCpaJbzA+fP00rEUhTqR4X6RrsaJaq7Y4GNshpERHbn Cn9Npq7INgIbLEyh19FbvvcrUOeldLJurZVi1wpnrQ+1NJGO9o+s4Kx3lIG9hxq5g5Oi NFjQ== X-Received: by 10.194.57.170 with SMTP id j10mr14487386wjq.102.1426171802715; Thu, 12 Mar 2015 07:50:02 -0700 (PDT) Received: from cizrna.lan ([109.72.12.88]) by mx.google.com with ESMTPSA id y14sm10349439wjr.39.2015.03.12.07.50.00 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Mar 2015 07:50:01 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Mikko Perttunen , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , Paul Walmsley , Peter De Schrijver , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 07/18] of: document external-memory-controller property in tegra124-car Date: Thu, 12 Mar 2015 15:47:59 +0100 Message-Id: <1426171746-26864-8-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1426171746-26864-1-git-send-email-tomeu.vizoso@collabora.com> References: <1426171746-26864-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This property contains a phandle to the EMC driver that is needed by the EMC clock to request the EMC driver to do its part of the clock change sequence. Signed-off-by: Tomeu Vizoso --- Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt index c3891ce..7f02fb4 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt @@ -20,6 +20,7 @@ Required properties : - #reset-cells : Should be 1. In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +- nvidia,external-memory-controller : phandle of the EMC driver. The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in register PMC_STRAPPING_OPT_A). @@ -50,6 +51,7 @@ Example SoC include file: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; usb@c5004000 {