From patchwork Wed Mar 11 10:34:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 448944 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 21E1514016B for ; Wed, 11 Mar 2015 21:41:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=Ylf7zkPI; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752469AbbCKKhA (ORCPT ); Wed, 11 Mar 2015 06:37:00 -0400 Received: from mail-wg0-f45.google.com ([74.125.82.45]:44058 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752446AbbCKKg5 (ORCPT ); Wed, 11 Mar 2015 06:36:57 -0400 Received: by wghl18 with SMTP id l18so8131347wgh.11; Wed, 11 Mar 2015 03:36:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=oHYh4ipnrHgAj7Ng7aQrHsJ9D+5uAQmDhUpoUA9cJlc=; b=Ylf7zkPIN0F6+mN9H61jeoJufq4G5e8VB8qOSE9cgsgRDwXzbpt93r7YjFK3unUS5V rf7xzabSLtw3paLGxWXjRrAe8cvV9tkt8sFxOwlW1i++tLYjQFvCXxecf94RjUC2h1uQ YSRRMvhm6YWOq7rwEVV/u5OhxdPHDktk2f0X2mh0Wp/frolzAOf6lHMLzuUR0I6I2/yJ 2rpmcQ6KbH4QZRD/DqHbmcPFgiAtZ36473NyJuDDilZavqpIp0ab3FZWGOiJLP7oNVd4 xE4h6cufAhizwtwLYe/VeEyWNAVasLxgKLx9O1JctNN2KqMBdx7QH+PB1qNMwOvGnqYm +aAQ== X-Received: by 10.180.106.42 with SMTP id gr10mr577698wib.73.1426070214930; Wed, 11 Mar 2015 03:36:54 -0700 (PDT) Received: from cizrna.lan ([109.72.12.53]) by mx.google.com with ESMTPSA id lj13sm5528244wic.9.2015.03.11.03.36.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Mar 2015 03:36:54 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Mikko Perttunen , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 05/18] of: Document timings subnode of nvidia,tegra-mc Date: Wed, 11 Mar 2015 11:34:18 +0100 Message-Id: <1426070126-26910-6-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1426070126-26910-1-git-send-email-tomeu.vizoso@collabora.com> References: <1426070126-26910-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MC driver needs some timing-specific information to program the EMEM during a rate change of the EMC clock. Signed-off-by: Tomeu Vizoso --- v4: * Add more information about nvidia,emem-configuration * Remove mandatory naming of the timings subnode * Remove constraint on the unit-address of the timings and timing subnodes --- .../memory-controllers/nvidia,tegra-mc.txt | 84 +++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt index f3db93c..3338a28 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt @@ -1,6 +1,9 @@ NVIDIA Tegra Memory Controller device tree bindings =================================================== +memory-controller node +---------------------- + Required properties: - compatible: Should be "nvidia,tegra-mc" - reg: Physical base address and length of the controller's registers. @@ -15,9 +18,49 @@ Required properties: This device implements an IOMMU that complies with the generic IOMMU binding. See ../iommu/iommu.txt for details. -Example: --------- +emc-timings subnode +------------------- + +The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in +register PMC_STRAPPING_OPT_A). + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for. + +timing subnode +-------------- + +Each "emc-timings" node should contain a subnode for every supported EMC clock rate. + +Required properties for timing nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC +(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be +specified, according to the board documentation: + + MC_EMEM_ARB_CFG + MC_EMEM_ARB_OUTSTANDING_REQ + MC_EMEM_ARB_TIMING_RCD + MC_EMEM_ARB_TIMING_RP + MC_EMEM_ARB_TIMING_RC + MC_EMEM_ARB_TIMING_RAS + MC_EMEM_ARB_TIMING_FAW + MC_EMEM_ARB_TIMING_RRD + MC_EMEM_ARB_TIMING_RAP2PRE + MC_EMEM_ARB_TIMING_WAP2PRE + MC_EMEM_ARB_TIMING_R2R + MC_EMEM_ARB_TIMING_W2W + MC_EMEM_ARB_TIMING_R2W + MC_EMEM_ARB_TIMING_W2R + MC_EMEM_ARB_DA_TURNS + MC_EMEM_ARB_DA_COVERS + MC_EMEM_ARB_MISC0 + MC_EMEM_ARB_MISC1 + MC_EMEM_ARB_RING1_THROTTLE +Example SoC include file: + +/ { mc: memory-controller@0,70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -34,3 +77,40 @@ Example: ... iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; }; +}; + +Example board file: + +/ { + memory-controller@0,70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; +};