From patchwork Wed Mar 11 10:34:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 448919 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6278714016B for ; Wed, 11 Mar 2015 21:36:52 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=i56BDgd0; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752375AbbCKKgr (ORCPT ); Wed, 11 Mar 2015 06:36:47 -0400 Received: from mail-wi0-f175.google.com ([209.85.212.175]:38652 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752002AbbCKKgm (ORCPT ); Wed, 11 Mar 2015 06:36:42 -0400 Received: by widex7 with SMTP id ex7so36995403wid.3; Wed, 11 Mar 2015 03:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=rwjiCGgez/cph2o9g6dk2ARI9PUVfStnzaF8Cn8IoWE=; b=i56BDgd0fj3pTa4OnyGf1Vt2dGizAHat05pqybM3o/L7GIBweF/cqxKmml7+vzOkLg So9xF2ZiVsLX4q/hBBEU3iH0hcvt/Nmro5tAzm1Rs+B3IVeg3AnKsjrUN9k992tlV4Lg Dsgwj9GmZMRXzyn5pE0V4lWii88PanUa1XnzMEmIIEYgk9ynq6uaKCKYS922+djXoawY et3ekL3fFWYb0Q8yclDz22TzX/zpkfQQzvFOC6ExP8HtFPqOmBtzfF/NUjagcO9kGw2E Rx7ddKVyJKxcB/yDO0ocYLaQnUYgxPd4HAchbthxMAGLyGUbbprvcqVIW2bNv43jdgXT BY1Q== X-Received: by 10.194.157.39 with SMTP id wj7mr38741294wjb.57.1426070200777; Wed, 11 Mar 2015 03:36:40 -0700 (PDT) Received: from cizrna.lan ([109.72.12.53]) by mx.google.com with ESMTPSA id lj13sm5528244wic.9.2015.03.11.03.36.38 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Mar 2015 03:36:39 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Mikko Perttunen , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , Eduardo Valentin , Peter De Schrijver , Paul Walmsley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 02/18] of: Document long-ram-code property in nvidia, tegra20-apbmisc Date: Wed, 11 Mar 2015 11:34:15 +0100 Message-Id: <1426070126-26910-3-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1426070126-26910-1-git-send-email-tomeu.vizoso@collabora.com> References: <1426070126-26910-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Needed to properly decode the ram code register. Signed-off-by: Tomeu Vizoso --- v3: * Clarify wording as suggested by Mikko --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index 47b205c..4556359 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -10,3 +10,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).