From patchwork Wed Feb 11 15:06:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 438836 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A53781402AA for ; Thu, 12 Feb 2015 02:08:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753447AbbBKPIV (ORCPT ); Wed, 11 Feb 2015 10:08:21 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:64886 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753217AbbBKPIS (ORCPT ); Wed, 11 Feb 2015 10:08:18 -0500 Received: by mail-wi0-f178.google.com with SMTP id em10so4403305wid.5; Wed, 11 Feb 2015 07:08:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=G3G1Iw+OOM4KN4AxwLKU6BOypniiQdLqsm/S7LvVBMs=; b=BH1m5zg3wCw0if3g0Z9xXLpmZ1EwefCUrv69RMExz01bhI8BgGIZu4cB3Rhg/H5dhP 2PtewEVdxxcK31Z78TImbm6Dp4VLmDoRyzVqjbU7U85sMwJeUNA4W0ffAw+wg4CJBcH3 Z+xfmjftuxlNCM2Pv0buVI9yNf4xea0J/VwBmRnvRJMeU4aagbOBFAKZik85NRtgl2Qc umTl0e8pnYkuqrrYx4hzYTDd/6ZTQtBT9dPiHD43ubcrDp8Ufmgo2ltCFSA6Q4fANCUp YEqrsU99WO1VdP7AO5SQu6mmstpW3SS+9cHM238uOEOyP/Es/4UAJPu5sarT8teaPEV+ BOUA== X-Received: by 10.194.62.52 with SMTP id v20mr13093021wjr.137.1423667295903; Wed, 11 Feb 2015 07:08:15 -0800 (PST) Received: from cizrna.lan (37-48-32-149.tmcz.cz. [37.48.32.149]) by mx.google.com with ESMTPSA id l4sm4662472wiw.9.2015.02.11.07.08.12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Feb 2015 07:08:15 -0800 (PST) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Stephen Warren , Javier Martinez Canillas , Simon Glass , Dylan Reid , Andrew Bresticker , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thierry Reding , Alexandre Courbot , Paul Walmsley , Eduardo Valentin , Mikko Perttunen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/11] ARM: tegra: add support for warm reset GPIO Date: Wed, 11 Feb 2015 16:06:41 +0100 Message-Id: <1423667220-1062-10-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1423667220-1062-1-git-send-email-tomeu.vizoso@collabora.com> References: <1423667220-1062-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andrew Bresticker Allow for a warm reset GPIO to be passed to the PMC driver via DT which will be used to reset the system instead of writing to PMC_CTRL. The GPIO will be asserted at reset time and, if this fails to reset the system, we'll fall back to using PMC_CTRL. Signed-off-by: Andrew Bresticker [tomeu.vizoso@collabora.com: Rebased] Signed-off-by: Tomeu Vizoso --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 1 + drivers/soc/tegra/pmc.c | 33 ++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index 02c2700..ee5568f 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -34,6 +34,7 @@ Optional properties: - nvidia,combined-power-req : Boolean, combined power request for CPU & Core - nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) is enabled. +- nvidia,reset-gpio : GPIO that can be used to warm reset the system. Required properties when nvidia,suspend-mode is specified: - nvidia,cpu-pwr-good-time : CPU power good time in uS. diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index c956395..effed0c 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -24,10 +24,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -127,6 +129,8 @@ struct tegra_pmc_soc { * @lp0_vec_phys: physical base address of the LP0 warm boot code * @lp0_vec_size: size of the LP0 warm boot code * @powergates_lock: mutex for power gate register access + * @reset_gpio: GPIO to assert to reset the system + * @reset_active_low: Reset GPIO is active-low */ struct tegra_pmc { struct device *dev; @@ -149,6 +153,9 @@ struct tegra_pmc { bool cpu_pwr_good_en; u32 lp0_vec_phys; u32 lp0_vec_size; + int reset_gpio; + bool reset_active_low; + struct mutex powergates_lock; }; @@ -386,6 +393,17 @@ void tegra_pmc_restart(enum reboot_mode mode, const char *cmd) { u32 value; + /* + * If there's a reset GPIO, attempt to use that first and then fall + * back to PMC reset if that fails. + */ + if (gpio_is_valid(pmc->reset_gpio)) { + value = pmc->reset_active_low ? 0 : 1; + gpio_direction_output(pmc->reset_gpio, value); + udelay(100); + pr_err("GPIO reset failed; using PMC reset...\n"); + } + value = tegra_pmc_readl(PMC_SCRATCH0); value &= ~PMC_SCRATCH0_MODE_MASK; @@ -629,6 +647,8 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) { u32 value, values[2]; + enum of_gpio_flags flags; + int err; if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { } else { @@ -695,6 +715,19 @@ static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) pmc->lp0_vec_phys = values[0]; pmc->lp0_vec_size = values[1]; + pmc->reset_gpio = of_get_named_gpio_flags(np, "nvidia,reset-gpio", + 0, &flags); + if (gpio_is_valid(pmc->reset_gpio)) { + err = gpio_request_one(pmc->reset_gpio, GPIOF_OUT_INIT_HIGH, + "soc-warm-reset"); + if (err) { + pr_err("Failed to request reset GPIO: %d\n", err); + pmc->reset_gpio = -1; + } + if (flags & OF_GPIO_ACTIVE_LOW) + pmc->reset_active_low = true; + } + return 0; }