From patchwork Sun Jan 18 22:27:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 430259 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 56F2F140272 for ; Mon, 19 Jan 2015 09:31:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751098AbbARWbi (ORCPT ); Sun, 18 Jan 2015 17:31:38 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:53302 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751081AbbARWbi (ORCPT ); Sun, 18 Jan 2015 17:31:38 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 7C27017F33BE1; Sun, 18 Jan 2015 22:31:32 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Sun, 18 Jan 2015 22:31:36 +0000 Received: from localhost (192.168.159.114) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Sun, 18 Jan 2015 22:31:26 +0000 From: Paul Burton To: CC: Paul Burton , Lars-Peter Clausen , Subject: [PATCH 07/36] devicetree: document ingenic,jz4740-intc binding Date: Sun, 18 Jan 2015 14:27:18 -0800 Message-ID: <1421620067-23933-8-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.2.1 In-Reply-To: <1421620067-23933-1-git-send-email-paul.burton@imgtec.com> References: <1421620067-23933-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.159.114] Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding documentation for the Ingenic jz4740 interrupt controller. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: devicetree@vger.kernel.org --- .../interrupt-controller/ingenic,jz4740-intc.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt new file mode 100644 index 0000000..3c06ef1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,jz4740-intc.txt @@ -0,0 +1,24 @@ +Ingenic jz4740 SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,jz4740-intc" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent: phandle of the CPU interrupt controller. +- interrupts - Specifies the CPU interrupt the controller is connected to. + +Example: + +intc: intc@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +};