From patchwork Wed Dec 24 08:22:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thloh@altera.com X-Patchwork-Id: 423873 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1380B140082 for ; Wed, 24 Dec 2014 19:56:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751514AbaLXI4V (ORCPT ); Wed, 24 Dec 2014 03:56:21 -0500 Received: from mail-by2on0088.outbound.protection.outlook.com ([207.46.100.88]:42315 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751790AbaLXI4U (ORCPT ); Wed, 24 Dec 2014 03:56:20 -0500 X-Greylist: delayed 1125 seconds by postgrey-1.27 at vger.kernel.org; Wed, 24 Dec 2014 03:56:19 EST Received: from BLUPR03MB213.namprd03.prod.outlook.com (10.255.212.145) by BLUPR03MB519.namprd03.prod.outlook.com (10.141.80.144) with Microsoft SMTP Server (TLS) id 15.1.49.12; Wed, 24 Dec 2014 08:22:47 +0000 Received: from BY2PR03CA056.namprd03.prod.outlook.com (10.141.249.29) by BLUPR03MB213.namprd03.prod.outlook.com (10.255.212.145) with Microsoft SMTP Server (TLS) id 15.1.49.12; Wed, 24 Dec 2014 08:22:46 +0000 Received: from BY2FFO11FD040.protection.gbl (2a01:111:f400:7c0c::167) by BY2PR03CA056.outlook.office365.com (2a01:111:e400:2c5d::29) with Microsoft SMTP Server (TLS) id 15.1.49.12 via Frontend Transport; Wed, 24 Dec 2014 08:22:45 +0000 Received: from sj-itexedge03.altera.priv.altera.com (66.35.236.227) by BY2FFO11FD040.mail.protection.outlook.com (10.1.14.225) with Microsoft SMTP Server (TLS) id 15.1.49.13 via Frontend Transport; Wed, 24 Dec 2014 08:22:45 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge03.altera.priv.altera.com (66.35.236.227) with Microsoft SMTP Server id 14.3.174.1; Wed, 24 Dec 2014 00:21:49 -0800 Received: from ubuntu (pg-thloh-l.altera.com [137.57.103.125]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with SMTP id sBO8Mcoa017218; Wed, 24 Dec 2014 00:22:39 -0800 (PST) Received: by ubuntu (sSMTP sendmail emulation); Wed, 24 Dec 2014 00:22:38 -0800 From: To: Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Linus Walleij , Alexandre Courbot , Grant Likely , Andrew Morton , "David S. Miller" , "Greg Kroah-Hartman" , Joe Perches , Mauro Carvalho Chehab , Antti Palosaari , , , CC: Dinh Nguyen , Tien Hock Loh Subject: [PATCH v8 1/2] drivers/gpio: Altera soft IP GPIO driver device tree binding Date: Wed, 24 Dec 2014 00:22:24 -0800 Message-ID: <1419409345-8297-2-git-send-email-thloh@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1419409345-8297-1-git-send-email-thloh@altera.com> References: <1419409345-8297-1-git-send-email-thloh@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning altera.com discourages use of 66.35.236.227 as permitted sender) Authentication-Results: spf=softfail (sender IP is 66.35.236.227) smtp.mailfrom=thloh@altera.com; X-Forefront-Antispam-Report: CIP:66.35.236.227; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(199003)(189002)(64706001)(46102003)(89996001)(105596002)(48376002)(47776003)(33646002)(62966003)(87936001)(19580405001)(50466002)(106466001)(120916001)(42186005)(20776003)(77156002)(6806004)(31966008)(19580395003)(4396001)(2950100001)(92566001)(2201001)(76176999)(50226001)(107046002)(86152002)(68736005)(84676001)(36756003)(229853001)(86362001)(21056001)(97736003)(50986999)(99396003)(7099022)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB213; H:sj-itexedge03.altera.priv.altera.com; FPR:; SPF:SoftFail; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: UriScan:;UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB213; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:BLUPR03MB213; X-Forefront-PRVS: 04359FAD81 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB213; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2014 08:22:45.1640 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a; Ip=[66.35.236.227] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB213 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB519; X-OriginatorOrg: altera.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tien Hock Loh Adds a new driver device tree binding for Altera soft GPIO IP Signed-off-by: Tien Hock Loh --- .../devicetree/bindings/gpio/gpio-altera.txt | 43 ++++++++++++++++++++ 1 files changed, 43 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-altera.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-altera.txt b/Documentation/devicetree/bindings/gpio/gpio-altera.txt new file mode 100644 index 0000000..649fa02 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-altera.txt @@ -0,0 +1,43 @@ +Altera GPIO controller bindings + +Required properties: +- compatible: + - "altr,pio-1.0" +- reg: Physical base address and length of the controller's registers. +- #gpio-cells : Should be 2 + - The first cell is the gpio offset number. + - The second cell is reserved and is currently unused. +- gpio-controller : Marks the device node as a GPIO controller. +- interrupt-controller: Mark the device node as an interrupt controller +- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware. + - The first cell is the GPIO offset number within the GPIO controller. +- interrupts: Specify the interrupt. +- altr,interrupt-trigger: Specifies the interrupt trigger type the GPIO + hardware is synthesized. This field is required if the Altera GPIO controller + used has IRQ enabled as the interrupt type is not software controlled, + but hardware synthesized. Required if GPIO is used as an interrupt + controller. The value is defined in + Only the following flags are supported: + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + IRQ_TYPE_LEVEL_HIGH + +Optional properties: +- altr,ngpio: Width of the GPIO bank. This defines how many pins the + GPIO device has. Ranges between 1-32. Optional and defaults to 32 is not + specified. + +Example: + +gpio_altr: gpio@0xff200000 { + compatible = "altr,pio-1.0"; + reg = <0xff200000 0x10>; + interrupts = <0 45 4>; + altr,ngpio = <32>; + altr,interrupt_trigger = ; + #gpio-cells = <1>; + gpio-controller; + #interrupt-cells = <1>; + interrupt-controller; +};