From patchwork Wed Nov 19 23:15:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 412543 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 71E6114010B for ; Thu, 20 Nov 2014 10:20:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933438AbaKSXUE (ORCPT ); Wed, 19 Nov 2014 18:20:04 -0500 Received: from mail-wg0-f50.google.com ([74.125.82.50]:64427 "EHLO mail-wg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756855AbaKSXQD (ORCPT ); Wed, 19 Nov 2014 18:16:03 -0500 Received: by mail-wg0-f50.google.com with SMTP id k14so2218577wgh.9 for ; Wed, 19 Nov 2014 15:16:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=DuH94meKoTBbYMVb8d8iGaQKluDj6M5Ndle0l6doxRA=; b=CFn9bvnytwwjPyMSKRO2ii0/GE7mfzB/YYyHAluejwrN1PpfKPMJkvBb30PSARjQFi 0BvWBrZrOKuL/fLY2tWQCW5MA9gRt7falXaCy/QXWjy27bxROWTm/W7ZY0GdNHScmHMA ZN0ZqL6M/p4NzJK4bt6WoIi18DRJcLbrYeQLufSjofyyobWnMW202s5NrfbP1rDcCZZu 0P1UUkBVKeyUPSt6BEvZSJMiC0TGlbyNUOEiBlAkjDNvBWSHbUz2Key5y+4bpVadLtp+ OhH7+sApBjOUJIK9blP5OlijYVQF62WbEFy1XcJlnobMhZMJM466Nib9ZQuL0WU1j9mt Zakg== X-Gm-Message-State: ALoCoQl2+9e3K8EDNyu1luJ3Uh9bAi1rEseXc0iAQE2u0nj8SRNzGWOjLVSwuI/d5bJQYEAAwM9+ X-Received: by 10.194.61.99 with SMTP id o3mr60939689wjr.54.1416438961478; Wed, 19 Nov 2014 15:16:01 -0800 (PST) Received: from radagast.localdomain (jahogan.plus.com. [212.159.75.221]) by mx.google.com with ESMTPSA id gi5sm797884wjd.26.2014.11.19.15.15.59 for (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Wed, 19 Nov 2014 15:16:00 -0800 (PST) From: James Hogan To: Mike Turquette , linux-metag@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: James Hogan , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH 03/15] dt: binding: add binding for tz1090-pll clock Date: Wed, 19 Nov 2014 23:15:31 +0000 Message-Id: <1416438943-11429-4-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1416438943-11429-1-git-send-email-james.hogan@imgtec.com> References: <1416438943-11429-1-git-send-email-james.hogan@imgtec.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add simple device tree binding for TZ1090 PLL clock. It takes a couple of registers, and has a single reference clock source. Signed-off-by: James Hogan Cc: Mike Turquette Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: linux-metag@vger.kernel.org Cc: devicetree@vger.kernel.org --- .../devicetree/bindings/clock/img,tz1090-pll.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/img,tz1090-pll.txt diff --git a/Documentation/devicetree/bindings/clock/img,tz1090-pll.txt b/Documentation/devicetree/bindings/clock/img,tz1090-pll.txt new file mode 100644 index 0000000..20aa622 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/img,tz1090-pll.txt @@ -0,0 +1,33 @@ +Binding for TZ1090 Phase-Lock Loop (PLL) clocks. + +This binding uses the common clock binding[1]. These PLLs are configured with 2 +registers specified with the reg property. These contain various fields which +among other things specify the reference divider value (r), the frequency +divider value (f), and the output divider value (od). When enabled, the output +clock rate is: + + f_out = f_ref / r * (f / 2) / od + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : Shall be "img,tz1090-pll". +- #clock-cells : From common clock binding; shall be set to 0. +- reg : Address of configuration register pair. +- clocks : From common clock binding. + +Required source clocks: +- 0 : Reference clock used to generate the output clock + (doesn't have to be named). + +Optional properties: +- clock-output-names : From common clock binding. + +Example: + sys_pll { + compatible = "img,tz1090-pll"; + #clock-cells = <0>; + clocks = <&sysclk0_sw>; + reg = <0x02005950 0x8>; /* CR_TOP_SYSPLL_CTL{0,1} */ + clock-output-names = "sys_pll"; + };