| Message ID | 1414599796-30597-3-git-send-email-tomeu.vizoso@collabora.com |
|---|---|
| State | Accepted, archived |
| Commit | 405990c7e834913554482538321f16f457dda50e |
| Headers | show |
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..d034ff8 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
Needed to properly decode the ram code register. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- v3: * Clarify wording as suggested by Mikko --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++ 1 file changed, 2 insertions(+)