From patchwork Fri Oct 10 12:46:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 398544 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4243F1400AB for ; Fri, 10 Oct 2014 23:53:59 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754051AbaJJMu6 (ORCPT ); Fri, 10 Oct 2014 08:50:58 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:44277 "EHLO mail-wi0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753400AbaJJMuz (ORCPT ); Fri, 10 Oct 2014 08:50:55 -0400 Received: by mail-wi0-f176.google.com with SMTP id hi2so1918275wib.15 for ; Fri, 10 Oct 2014 05:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Arq3hd9XzunA/hqGeZ7LrLjvA1Yxc9oOZjVLJLZ+Fx4=; b=QHZitT1aAYbDl6/qhrVTocdkJbGsuxvrErfgahiJPPzwclJJTMmW3OQStvEJMfSPpM zOyrJIFTnQNiC6wVB1Fn+ILwqczAfv1Ggh2GDZDVcgqEf5TjFdbx9CgKbfyMoc8ZTw2p V787PhdqAEpElhs2rRhuiwjJwArC0lggeIaheTFPfU4pztDhpwJD2Cyz0Y6haPkWIfPX vJMFPlm+7ejc8iokcBOSQ/9KAu96FlXaFbN9yPmRztPD41IHx+bajoby6Obk6fFoi6Et ELs+A0eMSA/X/lkHCeeJGmLjHRNhCaCMuMR38P+8DSmwTOWVlSJ8YGUj00/HhgRmDwyJ Y0Jg== X-Received: by 10.180.90.73 with SMTP id bu9mr4602523wib.57.1412945453485; Fri, 10 Oct 2014 05:50:53 -0700 (PDT) Received: from cizrna.lan (37-48-41-81.tmcz.cz. [37.48.41.81]) by mx.google.com with ESMTPSA id ua8sm6948661wjc.7.2014.10.10.05.50.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Oct 2014 05:50:52 -0700 (PDT) From: Tomeu Vizoso To: Stephen Warren Cc: Rhyland Klein , Mikko Perttunen , Thierry Reding , Javier Martinez Canillas , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Peter De Schrijver , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/10] soc/tegra: Document long-ram-code property in nvidia, tegra20-apbmisc Date: Fri, 10 Oct 2014 14:46:53 +0200 Message-Id: <1412945262-6068-3-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1412945262-6068-1-git-send-email-tomeu.vizoso@collabora.com> References: <1412945262-6068-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Tomeu Vizoso --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..e2562ed 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,6 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: boolean that tells whether the ram code is long (4 bit) + or short (2 bit). If not present, false.