From patchwork Tue Feb 11 11:37:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 319230 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B483E2C00AE for ; Tue, 11 Feb 2014 22:38:33 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751303AbaBKLic (ORCPT ); Tue, 11 Feb 2014 06:38:32 -0500 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:50082 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750969AbaBKLib (ORCPT ); Tue, 11 Feb 2014 06:38:31 -0500 Received: from e106331-lin.cambridge.arm.com (e106331-lin.cambridge.arm.com [10.1.205.154]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s1BBbFkj008527; Tue, 11 Feb 2014 11:38:01 GMT From: Mark Rutland To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, pawel.moll@arm.com, Mark Rutland , Russell King , Arnd Bergmann Subject: [PATCH 1/7] Documentation: devicetree: fix up pl011 clocks Date: Tue, 11 Feb 2014 11:37:06 +0000 Message-Id: <1392118632-11312-2-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1392118632-11312-1-git-send-email-mark.rutland@arm.com> References: <1392118632-11312-1-git-send-email-mark.rutland@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The "arm,pl011" device tree binding only describes the apb_pclk clock input, which is not sufficient to use the device. Knowledge of the uartclk clock input is required to be able to change the baud rate, as the baud rate is derived from the reference uartclk input. On systems where the uartclk input is not initially enabled, it is also required to use the device in any fashion. This patch adds the uartclk input to the pl011 device tree binding. The clock-names property is also described, as it is an implied requirement of the primecell binding the pl011 binding is derived from. Signed-off-by: Mark Rutland Cc: Russell King Cc: Arnd Bergmann Cc: Rob Herring Cc: Pawel Moll --- Documentation/devicetree/bindings/serial/pl011.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index 5d2e840..f0a9e77 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -8,8 +8,10 @@ Required properties: Optional properties: - pinctrl: When present, must have one state named "sleep" and one state named "default" -- clocks: When present, must refer to exactly one clock named - "apb_pclk" +- clocks: When present, must refer to a clock named + "apb_pclk", and optionally "uartclk". +- clock-names: When present, should include "apb_pclk" and + "uartclk", matching the clocks property. - dmas: When present, may have one or two dma channels. The first one must be named "rx", the second one must be named "tx".