From patchwork Fri Jan 31 21:46:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: achew@nvidia.com X-Patchwork-Id: 315848 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E17992C00AE for ; Sat, 1 Feb 2014 08:46:52 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932797AbaAaVqW (ORCPT ); Fri, 31 Jan 2014 16:46:22 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9142 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754449AbaAaVqV (ORCPT ); Fri, 31 Jan 2014 16:46:21 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 31 Jan 2014 13:46:41 -0800 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 31 Jan 2014 13:45:07 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 31 Jan 2014 13:45:07 -0800 Received: from achew-linux64.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.327.1; Fri, 31 Jan 2014 13:46:20 -0800 From: Andrew Chew To: , , , , , , , , , , CC: , , , , Andrew Chew Subject: [PATCH v1] ARM: tegra: add nvidia,wdt-timer-id optional property Date: Fri, 31 Jan 2014 13:46:51 -0800 Message-ID: <1391204811-6293-1-git-send-email-achew@nvidia.com> X-Mailer: git-send-email 1.8.1.5 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This optional property can be used to specify which timers are to be used for hardware watchdog timeouts (via a tegra wdt driver). Signed-off-by: Andrew Chew --- Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt index b5082a1..e87fa70 100644 --- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt @@ -13,6 +13,13 @@ Required properties: - clocks : Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. +Optional properties: + +- nvidia,wdt-timer-id: A list of timer IDs to be used for watchdogs. + Watchdog 0 will be assigned to the first timer listed, watchdog 1 will + be assigned to the second timer listed, etc. up to the number of watchdogs + available. + timer { compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; @@ -23,4 +30,5 @@ timer { 0 121 0x04 0 122 0x04>; clocks = <&tegra_car 214>; + nvidia,wdt-timer-id = <7 8>; };