[7/7] clk/exynos5260: add clock file for exynos5260

Message ID	1386345391-23482-8-git-send-email-rahul.sharma@samsung.com
State	Superseded, archived
Headers	show Return-Path: <devicetree-owner@vger.kernel.org> From: Rahul Sharma <rahul.sharma@samsung.com> To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, thomas.ab@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, pankaj.dubey@samsung.com, yg1004.jang@samsung.com, arun.kk@samsung.com, r.sh.open@gmail.com, Rahul Sharma <rahul.sharma@samsung.com> Subject: [PATCH 7/7] clk/exynos5260: add clock file for exynos5260 Date: Fri, 06 Dec 2013 21:26:31 +0530 Message-id: <1386345391-23482-8-git-send-email-rahul.sharma@samsung.com> In-reply-to: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> References: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> DLP-Filter: Pass Sender: devicetree-owner@vger.kernel.org Precedence: bulk

diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file mode 100644 index 0000000..b5c021c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt @@ -0,0 +1,228 @@ +* Samsung Exynos5260 Clock Controller + +The Exynos5260 clock controller encalsulate all CMUs which are +instantiaited independently from the device-tree. As a whole, +these CMUs generates and supplies clocks to various controllers +within the Exynos5260 SoC. + +Required Properties: + +- compatible: should be one of the following. + - First compatible should be one of the following + "exynos5260-cmu-all" + "exynos5260-cmu-top" + "exynos5260-cmu-peri" + "exynos5260-cmu-egl" + "exynos5260-cmu-kfc" + "exynos5260-cmu-g2d" + "exynos5260-cmu-mif" + "exynos5260-cmu-mfc" + "exynos5260-cmu-g3d" + "exynos5260-cmu-fsys" + "exynos5260-cmu-aud" + "exynos5260-cmu-isp" + "exynos5260-cmu-gscl" + "exynos5260-cmu-disp" + - Second compatible should be "samsung,exynos5260-clock". + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the each controller. Each +clock is assigned a MACRO constant. These constants are defined in +"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to specify +the clock which they consume. + +----------------------- + CMU_TOP clocks +----------------------- + + FIN_PLL + TOP_FOUT_DISP_PLL + TOP_FOUT_AUD_PLL + TOP_SCLK_MMC0 + TOP_SCLK_MMC1 + TOP_SCLK_MMC2 + TOP_SCLK_HDMIPHY + TOP_SCLK_FIMD1 + TOP_MOUT_FIMD1 + TOP_MOUT_DISP_PLL + +----------------------- + CMU_EGL clocks +----------------------- + + EGL_FOUT_EGL_PLL + EGL_FOUT_EGL_DPLL + +----------------------- + CMU_KFC clocks +----------------------- + + KFC_FOUT_KFC_PLL + +----------------------- + CMU_MIF clocks +----------------------- + + MIF_FOUT_MEM_PLL + MIF_FOUT_BUS_PLL + MIF_FOUT_MEDIA_PLL + +----------------------- + CMU_G3D clocks +----------------------- + + G3D_FOUT_G3D_PLL + G3D_ACLK_G3D + +----------------------- + CMU_AUD clocks +----------------------- + + AUD_SCLK_AUD_UART + AUD_SCLK_PCM + AUD_ACLK_SRAMC + AUD_ACLK_DMAC + AUD_PCLK_AUD_UART + AUD_PCLK_PCM + AUD_PCLK_I2S + AUD_PCLK_DMAC + +----------------------- + CMU_MFC clocks +----------------------- + + MFC_ACLK_MFC + MFC_PCLK_MFC + MFC_PCLK_SMMU_MFC0 + MFC_PCLK_SMMU_MFC1 + +----------------------- + CMU_GSCL clocks +----------------------- + + GSCL_ACLK_GSCL0 + GSCL_ACLK_GSCL1 + GSCL_PCLK_GSCL0 + GSCL_PCLK_GSCL1 + GSCL_PCLK_SMMU_GSCL0 + GSCL_PCLK_SMMU_GSCL1 + +----------------------- + CMU_FSYS clocks +----------------------- + + FSYS_HCLK_TSI + FSYS_PCLK_GPIO + FSYS_HCLK_USBHOST20 + FSYS_ACLK_USBDRD30 + FSYS_ACLK_PDMA0 + FSYS_ACLK_RTIC + FSYS_PCLK_SMMU_RTIC + FSYS_PHYCLK_USBDRD30 + FSYS_PHYCLK_USBHOST20 + FSYS_HCLK_MMC0 + FSYS_HCLK_MMC1 + FSYS_HCLK_MMC2 + FSYS_HCLK_SROMC + +----------------------- + CMU_PERI clocks +----------------------- + + PERI_PCLK_ADC + PERI_PCLK_TMU1 + PERI_PCLK_TMU0 + PERI_PCLK_SPI0 + PERI_PCLK_SPI1 + PERI_PCLK_SPI2 + PERI_PCLK_I2S1 + PERI_PCLK_PWM + PERI_PCLK_SPDIF + PERI_PCLK_ABB + PERI_PCLK_MCT + PERI_PCLK_HSIC0 + PERI_PCLK_HSIC1 + PERI_PCLK_HSIC2 + PERI_PCLK_HSIC3 + PERI_PCLK_UART0 + PERI_PCLK_UART1 + PERI_PCLK_UART2 + PERI_PCLK_PCM1 + PERI_PCLK_WDT_EGL + PERI_PCLK_WDT_KFC + PERI_PCLK_CHIPID + PERI_CLK_TMU0 + PERI_CLK_TMU1 + PERI_CLK_TMU2 + PERI_CLK_TMU3 + PERI_CLK_TMU4 + PERI_PCLK_I2C4 + PERI_PCLK_I2C5 + PERI_PCLK_I2C6 + PERI_PCLK_I2C7 + PERI_PCLK_I2C8 + PERI_PCLK_I2C9 + PERI_PCLK_I2C10 + PERI_PCLK_I2C11 + PERI_PCLK_TOP_RTC + PERI_SCLK_RTC + PERI_SCLK_UART0 + PERI_SCLK_UART1 + PERI_SCLK_UART2 + PERI_SCLK_SPDIF + PERI_SCLK_SPI0 + PERI_SCLK_SPI1 + PERI_SCLK_SPI2 + PERI_SCLK_I2S + PERI_SCLK_PCM1 + +----------------------- + CMU_DISP clocks +----------------------- + + DISP_SCLK_HDMI + DISP_SCLK_PIXEL + DISP_ACLK_MIXER + DISP_ACLK_HDMI + DISP_ACLK_FIMD1 + DISP_PCLK_SMMU_TV + DISP_PCLK_SMMU_FIMD1M1 + DISP_PCLK_SMMU_FIMD1M0 + DISP_PCLK_DSIM1 + DISP_PCLK_HDMIPHY + DISP_PCLK_HDMI + DISP_DP + DISP_MOUT_HDMI_PHY_PIXEL + +----------------------- + CMU_G2D clocks +----------------------- + + G2D_ACLK_MDMA + G2D_NR_CLK + +Example 1: An example of a clock controller node is listed below. + + cmu_disp: clock-controller@0x14550000 { + compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the + peri clock controller. Refer to the standard clock bindings for + information about 'clocks' and 'clock-names' property. + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..f791b31 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c new file mode 100644 index 0000000..c5814ad --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -0,0 +1,2661 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5260 SoC. +*/ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> + +#include "clk-exynos5260.h" +#include "clk.h" +#include "clk-pll.h" + +#include <dt-bindings/clk/exynos5260-clk.h> + +static LIST_HEAD(clock_reg_cache_list); + +struct exynos5260_clock_reg_cache { + struct list_head node; + void __iomem *reg_base; + struct samsung_clk_reg_dump *rdump; + unsigned int rd_num; +}; + +#ifdef CONFIG_PM_SLEEP + +/* + * list of controller registers to be saved and restored during a + * suspend/resume cycle. +*/ + +static struct samsung_clk_reg_dump exynos5260_aud_clk_regs[] __initdata = { +/* + *Registers for CMU_AUD +*/ + { MUX_SEL_AUD, 0}, + { DIV_AUD0, 0}, + { DIV_AUD1, 0}, + { EN_ACLK_AUD, 0}, + { EN_PCLK_AUD, 0}, + { EN_SCLK_AUD, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_disp_clk_regs[] __initdata = { +/* + *Registers for CMU_DISP +*/ + { MUX_SEL_DISP0, 0}, + { MUX_SEL_DISP1, 0}, + { MUX_SEL_DISP2, 0}, + { MUX_SEL_DISP3, 0}, + { MUX_SEL_DISP4, 0}, + { DIV_DISP, 0}, + { EN_ACLK_DISP, 0}, + { EN_PCLK_DISP, 0}, + { EN_SCLK_DISP0, 0}, + { EN_SCLK_DISP1, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_egl_clk_regs[] __initdata = { +/* + *Registers for CMU_EGL +*/ + { EGL_PLL_LOCK, 0}, + { EGL_PLL_CON0, 0}, + { EGL_PLL_CON1, 0}, + { EGL_PLL_FREQ_DET, 0}, + + { MUX_SEL_EGL, 0}, + { MUX_ENABLE_EGL, 0}, + { DIV_EGL, 0}, + { DIV_EGL_PLL_FDET, 0}, + { EN_ACLK_EGL, 0}, + { EN_PCLK_EGL, 0}, + { EN_SCLK_EGL, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_fsys_clk_regs[] __initdata = { +/* + *Registers for CMU_FSYS +*/ + { MUX_SEL_FSYS0, 0}, + { MUX_SEL_FSYS1, 0}, + { EN_ACLK_FSYS, 0}, + { EN_ACLK_FSYS_SECURE_RTIC, 0}, + { EN_ACLK_FSYS_SECURE_SMMU_RTIC, 0}, + { EN_SCLK_FSYS, 0}, + { EN_IP_FSYS, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_g2d_clk_regs[] __initdata = { +/* + *Registers for CMU_G2D +*/ + { MUX_SEL_G2D, 0}, + { MUX_STAT_G2D, 0}, + { DIV_G2D, 0}, + { EN_ACLK_G2D, 0}, + { EN_ACLK_G2D_SECURE_SSS, 0}, + { EN_ACLK_G2D_SECURE_SLIM_SSS, 0}, + { EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 0}, + { EN_ACLK_G2D_SECURE_SMMU_SSS, 0}, + { EN_ACLK_G2D_SECURE_SMMU_MDMA, 0}, + { EN_ACLK_G2D_SECURE_SMMU_G2D, 0}, + { EN_PCLK_G2D, 0}, + { EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 0}, + { EN_PCLK_G2D_SECURE_SMMU_SSS, 0}, + { EN_PCLK_G2D_SECURE_SMMU_MDMA, 0}, + { EN_PCLK_G2D_SECURE_SMMU_G2D, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_g3d_clk_regs[] __initdata = { +/* + *Registers for CMU_G3D +*/ + { G3D_PLL_LOCK, 0}, + { G3D_PLL_CON0, 0}, + { G3D_PLL_CON1, 0}, + { G3D_PLL_FDET, 0}, + { MUX_SEL_G3D, 0}, + { DIV_G3D, 0}, + { DIV_G3D_PLL_FDET, 0}, + { EN_ACLK_G3D, 0}, + { EN_PCLK_G3D, 0}, + { EN_SCLK_G3D, 0}, + { EN_IP_G3D, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_gscl_clk_regs[] __initdata = { +/* + *Registers for CMU_GSCL +*/ + { MUX_SEL_GSCL, 0}, + { DIV_GSCL, 0}, + { EN_ACLK_GSCL, 0}, + { EN_ACLK_GSCL_FIMC, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 0}, + { EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 0}, + { EN_PCLK_GSCL, 0}, + { EN_PCLK_GSCL_FIMC, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 0}, + { EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 0}, + { EN_SCLK_GSCL, 0}, + { EN_SCLK_GSCL_FIMC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_isp_clk_regs[] __initdata = { +/* + *Registers for CMU_ISP +*/ + { MUX_SEL_ISP0, 0}, + { MUX_SEL_ISP1, 0}, + { DIV_ISP, 0}, + { EN_ACLK_ISP0, 0}, + { EN_ACLK_ISP1, 0}, + { EN_PCLK_ISP0, 0}, + { EN_PCLK_ISP1, 0}, + { EN_SCLK_ISP, 0}, + { EN_IP_ISP0, 0}, + { EN_IP_ISP1, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_kfc_clk_regs[] __initdata = { +/* + *Registers for CMU_KFC +*/ + { KFC_PLL_LOCK, 0}, + { KFC_PLL_CON0, 0}, + { KFC_PLL_CON1, 0}, + { KFC_PLL_FDET, 0}, + { MUX_SEL_KFC0, 0}, + { MUX_SEL_KFC2, 0}, + { DIV_KFC, 0}, + { DIV_KFC_PLL_FDET, 0}, + { EN_ACLK_KFC, 0}, + { EN_PCLK_KFC, 0}, + { EN_SCLK_KFC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_mfc_clk_regs[] __initdata = { +/* + *Registers for CMU_MFC +*/ + { MUX_SEL_MFC, 0}, + { DIV_MFC, 0}, + { EN_ACLK_MFC, 0}, + { EN_ACLK_SECURE_SMMU2_MFC, 0}, + { EN_PCLK_MFC, 0}, + { EN_PCLK_SECURE_SMMU2_MFC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_mif_clk_regs[] __initdata = { +/* + *Registers for CMU_MIF +*/ + { MEM_PLL_LOCK, 0}, + { BUS_PLL_LOCK, 0}, + { MEDIA_PLL_LOCK, 0}, + { MEM_PLL_CON0, 0}, + { MEM_PLL_CON1, 0}, + { MEM_PLL_FDET, 0}, + { BUS_PLL_CON0, 0}, + { BUS_PLL_CON1, 0}, + { BUS_PLL_FDET, 0}, + { MEDIA_PLL_CON0, 0}, + { MEDIA_PLL_CON1, 0}, + { MEDIA_PLL_FDET, 0}, + { MUX_SEL_MIF, 0}, + { DIV_MIF, 0}, + { DIV_MIF_PLL_FDET, 0}, + { EN_ACLK_MIF, 0}, + { EN_ACLK_MIF_SECURE_DREX1_TZ, 0}, + { EN_ACLK_MIF_SECURE_DREX0_TZ, 0}, + { EN_ACLK_MIF_SECURE_INTMEM, 0}, + { EN_PCLK_MIF, 0}, + { EN_PCLK_MIF_SECURE_MONOCNT, 0}, + { EN_PCLK_MIF_SECURE_RTC_APBIF, 0}, + { EN_PCLK_MIF_SECURE_DREX1_TZ, 0}, + { EN_PCLK_MIF_SECURE_DREX0_TZ, 0}, + { EN_SCLK_MIF, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_peri_clk_regs[] __initdata = { +/* + *Registers for CMU_PERI +*/ + { MUX_SEL_PERI, 0}, + { MUX_SEL_PERI1, 0}, + { DIV_PERI, 0}, + { EN_PCLK_PERI0, 0}, + { EN_PCLK_PERI1, 0}, + { EN_PCLK_PERI2, 0}, + { EN_PCLK_PERI3, 0}, + { EN_PCLK_PERI_SECURE_CHIPID, 0}, + { EN_PCLK_PERI_SECURE_PROVKEY0, 0}, + { EN_PCLK_PERI_SECURE_PROVKEY1, 0}, + { EN_PCLK_PERI_SECURE_SECKEY, 0}, + { EN_PCLK_PERI_SECURE_ANTIRBKCNT, 0}, + { EN_PCLK_PERI_SECURE_TOP_RTC, 0}, + { EN_PCLK_PERI_SECURE_TZPC, 0}, + { EN_SCLK_PERI, 0}, + { EN_SCLK_PERI_SECURE_TOP_RTC, 0}, +}; + +static struct samsung_clk_reg_dump exynos5260_top_clk_regs[] __initdata = { +/* + *Registers for CMU_TOP +*/ + { DISP_PLL_LOCK, 0}, + { AUD_PLL_LOCK, 0}, + { DISP_PLL_CON0, 0}, + { DISP_PLL_CON1, 0}, + { DISP_PLL_FDET, 0}, + { AUD_PLL_CON0, 0}, + { AUD_PLL_CON1, 0}, + { AUD_PLL_CON2, 0}, + { AUD_PLL_FDET, 0}, + { MUX_SEL_TOP_PLL0, 0}, + { MUX_SEL_TOP_MFC, 0}, + { MUX_SEL_TOP_G2D, 0}, + { MUX_SEL_TOP_GSCL, 0}, + { MUX_SEL_TOP_ISP10, 0}, + { MUX_SEL_TOP_ISP11, 0}, + { MUX_SEL_TOP_DISP0, 0}, + { MUX_SEL_TOP_DISP1, 0}, + { MUX_SEL_TOP_BUS, 0}, + { MUX_SEL_TOP_PERI0, 0}, + { MUX_SEL_TOP_PERI1, 0}, + { MUX_SEL_TOP_FSYS, 0}, + { DIV_TOP_G2D_MFC, 0}, + { DIV_TOP_GSCL_ISP0, 0}, + { DIV_TOP_ISP10, 0}, + { DIV_TOP_ISP11, 0}, + { DIV_TOP_DISP, 0}, + { DIV_TOP_BUS, 0}, + { DIV_TOP_PERI0, 0}, + { DIV_TOP_PERI1, 0}, + { DIV_TOP_PERI2, 0}, + { DIV_TOP_FSYS0, 0}, + { DIV_TOP_FSYS1, 0}, + { DIV_TOP_HPM, 0}, + { DIV_TOP_PLL_FDET, 0}, + { EN_ACLK_TOP, 0}, + { EN_SCLK_TOP, 0}, +}; + +static int exynos5260_clk_suspend(void) +{ + struct exynos5260_clock_reg_cache *cache; + + list_for_each_entry(cache, &clock_reg_cache_list, node) + samsung_clk_save(cache->reg_base, cache->rdump, + cache->rd_num); + + return 0; +} + +static void exynos5260_clk_resume(void) +{ + struct exynos5260_clock_reg_cache *cache; + + list_for_each_entry(cache, &clock_reg_cache_list, node) + samsung_clk_restore(cache->reg_base, cache->rdump, + cache->rd_num); +} + +static struct syscore_ops exynos5260_clk_syscore_ops = { + .suspend = exynos5260_clk_suspend, + .resume = exynos5260_clk_resume, +}; + +static void exynos5260_clk_sleep_init(void __iomem *reg_base, + struct samsung_clk_reg_dump *rdump, + unsigned long nr_rdump) +{ + struct exynos5260_clock_reg_cache *reg_cache; + + reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache), + GFP_KERNEL); + if (!reg_cache) + panic("could not allocate register cache.\n"); + + reg_cache->reg_base = reg_base; + reg_cache->rdump = rdump; + reg_cache->rd_num = nr_rdump; + list_add_tail(&reg_cache->node, &clock_reg_cache_list); + + register_syscore_ops(&exynos5260_clk_syscore_ops); + + exynos5260_clk_suspend(); +} + +#else +static void exynos5260_clk_sleep_init(void) {} +#endif + +/* + * List of parent clocks for muses in CMU_AUD +*/ +PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"}; +PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"}; + +/* + * List of parent clocks for muses in CMU_DISP +*/ +PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch3_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch2_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch1_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch0_txd_clk"}; + +PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"}; +PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"}; +PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"}; +PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_tmds_clko"}; +PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_ref_clko"}; +PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_pixel_clko"}; +PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll", + "phyclk_hdmi_link_o_tmds_clkhi"}; +PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll", + "phyclk_mipi_dphy_4l_m_txbyte_clkhs"}; +PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll", + "phyclk_dptx_phy_o_ref_clk_24m"}; +PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll", + "phyclk_dptx_phy_clk_div2"}; +PNAME(mout_sclk_dsim1_tx_clk_esc_clk_user_p) = {"fin_pll", + "sclk_dsim1_txclkescclk"}; +PNAME(mout_sclk_dsim1_tx_clk_esc3_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc3"}; +PNAME(mout_sclk_dsim1_tx_clk_esc2_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc2"}; +PNAME(mout_sclk_dsim1_tx_clk_esc1_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc1"}; +PNAME(mout_sclk_dsim1_tx_clk_esc0_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc0"}; +PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user", + "mout_aclk_disp_222_user"}; +PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", + "phyclk_mipi_dphy_4l_m_rxclkesc0"}; +PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", + "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; + +/* + * List of parent clocks for muses in CMU_EGL +*/ +PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; +PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; + +/* + * List of parent clocks for muses in CMU_FSYS +*/ +PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_phyclock"}; +PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_freeclk"}; +PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_clk48mohci"}; +PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", + "phyclk_usbdrd30_udrd30_pipe_pclk"}; +PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", + "phyclk_usbdrd30_udrd30_phyclock"}; + +/* + * List of parent clocks for muses in CMU_G2D +*/ +PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; + +/* + * List of parent clocks for muses in CMU_G3D +*/ +PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; + +/* + * List of parent clocks for muses in CMU_GSCL +*/ +PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; +PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; +PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; + +/* + * List of parent clocks for muses in CMU_ISP +*/ +PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; +PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; + +/* + * List of parent clocks for muses in CMU_KFC +*/ +PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; +PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; + +/* + * List of parent clocks for muses in CMU_MFC +*/ +PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; + +/* + * List of parent clocks for muses in CMU_MIF +*/ +PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; +PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"}; +PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"}; +PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"}; +PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; +PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; +PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; + +/* + * List of parent clocks for muses in CMU_PERI +*/ +PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud", + "phyclk_hdmi_phy_ref_cko"}; +PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", + "phyclk_hdmi_phy_ref_cko"}; +PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extlk", "fin_pll", + "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; + +/* + * List of parent clocks for muses in CMU_TOP +*/ +PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"}; +PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"}; +PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"}; +PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"}; +PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"}; + +PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"}; + +PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"}; + +PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user", + "mout_gscl_bustop_333"}; +PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user", + "mout_m2m_mediatop_400"}; +PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user", + "mout_gscl_bustop_fimc"}; + +PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user", + "mout_memtop_pll_user"}; +PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"}; +PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"}; + +PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"}; + +PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; +PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"}; +PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; +PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"}; +PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user", + "mout_bustop_pll_user"}; +PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"}; + +PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; +PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; + +PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"}; + +PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a", + "mout_mediatop_pll_user"}; +PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", + "mout_mediatop_pll_user"}; +PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", + "mout_mediatop_pll_user"}; + +/* fixed rate clocks generated outside the soc */ +struct samsung_fixed_rate_clock exynos5260_fixed_rate_ext_clks[] __initdata = { + FRATE(FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "xrtcxti", NULL, CLK_IS_ROOT, 32768), + + FRATE(ID_NONE, "ioclk_audcdclk0_user", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_pcm_extclk", NULL, CLK_IS_ROOT, 2048000), + FRATE(ID_NONE, "ioclk_aud_i2s_bclk", NULL, CLK_IS_ROOT, 2048000), + FRATE(ID_NONE, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 49152000), + FRATE(ID_NONE, "ioclk_i2s_cdclk", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spdif_extlk", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_i2s_sclk", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi0_clkin", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi1_clkin", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi2_clkin", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_mmc0_sdrdqs_in", NULL, CLK_IS_ROOT, 200000000), + + FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_in", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_in", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_out", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_out", NULL, + CLK_IS_ROOT, 50000000), +}; + +/* fixed rate clocks generated inside the soc */ +struct samsung_fixed_rate_clock exynos5260_fixed_rate_clks[] __initdata = { + FRATE(ID_NONE, "phyclk_dptx_phy_ch3_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch2_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch1_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch0_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_hdmi_phy_tmds_clko", NULL, + CLK_IS_ROOT, 250000000), + FRATE(TOP_SCLK_HDMIPHY, "phyclk_hdmi_phy_pixel_clko", NULL, + CLK_IS_ROOT, 1660000000), + FRATE(ID_NONE, "phyclk_hdmi_link_o_tmds_clkhi", NULL, + CLK_IS_ROOT, 125000000), + FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_txbyteclkhs", NULL, + CLK_IS_ROOT, 187500000), + FRATE(ID_NONE, "phyclk_dptx_phy_o_ref_clk_24m", NULL, + CLK_IS_ROOT, 24000000), + FRATE(ID_NONE, "phyclk_dptx_phy_clk_div2", NULL, + CLK_IS_ROOT, 135000000), + FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, + CLK_IS_ROOT, 20000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_phyclock", NULL, + CLK_IS_ROOT, 60000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_freeclk", NULL, + CLK_IS_ROOT, 60000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_clk48mohci", NULL, + CLK_IS_ROOT, 48000000), + FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, + CLK_IS_ROOT, 125000000), + FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_phyclock", NULL, + CLK_IS_ROOT, 60000000), +}; + +struct samsung_fixed_factor_clock exynos5260_fixed_factor_clks[] __initdata = { +}; + +/* MULITPLEXER CLOCKS */ + +/* + * List of Mux clocks for CMU_AUD +*/ +struct samsung_mux_clock exynos5260_aud_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, + MUX_SEL_AUD, 8, 1), + MUX(ID_NONE, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, MUX_SEL_AUD, 4, + 1), + MUX(ID_NONE, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 0, + 1), +}; + +/* + * List of Mux clocks for CMU_DISP +*/ +struct samsung_mux_clock exynos5260_disp_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_hdmi_spdif", mout_sclk_hdmi_spdif_p, + MUX_SEL_DISP4, 4, 2), + + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc_clk_user", + mout_sclk_dsim1_tx_clk_esc_clk_user_p, + MUX_SEL_DISP2, 28, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc3_user", + mout_sclk_dsim1_tx_clk_esc3_user_p, MUX_SEL_DISP2, + 24, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc2_user", + mout_sclk_dsim1_tx_clk_esc2_user_p, MUX_SEL_DISP2, + 20, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc1_user", + mout_sclk_dsim1_tx_clk_esc1_user_p, MUX_SEL_DISP2, + 16, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc0_user", + mout_sclk_dsim1_tx_clk_esc0_user_p, MUX_SEL_DISP2, + 12, 1), + MUX(ID_NONE, "mout_sclk_hdmi_pixel", mout_sclk_hdmi_pixel_p, + MUX_SEL_DISP2, 4, 1), + MUX(ID_NONE, "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", + mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p, + MUX_SEL_DISP2, 0, 1), + + MUX(ID_NONE, "mout_phyclk_hdmi_phy_tmds_clko_user", + mout_phyclk_hdmi_phy_tmds_clko_user_p, + MUX_SEL_DISP1, 28, 1), + MUX(ID_NONE, "mout_phyclk_hdmi_phy_ref_clko_user", + mout_phyclk_hdmi_phy_ref_clko_user_p, + MUX_SEL_DISP1, 24, 1), + MUX(DISP_MOUT_HDMI_PHY_PIXEL, "mout_phyclk_hdmi_phy_pixel_clko_user", + mout_phyclk_hdmi_phy_pixel_clko_user_p, + MUX_SEL_DISP1, 20, 1), + MUX(ID_NONE, "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + mout_phyclk_hdmi_link_o_tmds_clkhi_user_p, + MUX_SEL_DISP1, 16, 1), + MUX(ID_NONE, "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", + mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, + MUX_SEL_DISP1, 8, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_o_ref_clk_24m_user", + mout_phyclk_dptx_phy_o_ref_clk_24m_user_p, + MUX_SEL_DISP1, 4, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_clk_div2_user", + mout_phyclk_dptx_phy_clk_div2_user_p, + MUX_SEL_DISP1, 0, 1), + + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch3_txd_clk_user", + mout_phyclk_dptx_phy_ch3_txd_clk_user_p, + MUX_SEL_DISP0, 28, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch2_txd_clk_user", + mout_phyclk_dptx_phy_ch2_txd_clk_user_p, + MUX_SEL_DISP0, 24, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch1_txd_clk_user", + mout_phyclk_dptx_phy_ch1_txd_clk_user_p, + MUX_SEL_DISP0, 20, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch0_txd_clk_user", + mout_phyclk_dptx_phy_ch0_txd_clk_user_p, + MUX_SEL_DISP0, 16, 1), + MUX(ID_NONE, "mout_aclk_disp_222_user", mout_aclk_disp_222_user_p, + MUX_SEL_DISP0, 8, 1), + MUX(ID_NONE, "mout_sclk_disp_pixel_user", mout_sclk_disp_pixel_user_p, + MUX_SEL_DISP0, 4, 1), + MUX(ID_NONE, "mout_aclk_disp_333_user", mout_aclk_disp_333_user_p, + MUX_SEL_DISP0, 0, 1), +}; + +/* + * List of Mux clocks for CMU_EGL +*/ +struct samsung_mux_clock exynos5260_egl_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), + MUX(ID_NONE, "mout_egl_pll", mout_egl_pll_p, MUX_SEL_EGL, 4, 1), +}; + +/* + * List of Mux clocks for CMU_FSYS +*/ +struct samsung_mux_clock exynos5260_fsys_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_phyclk_usbhost20_phyclk_user", + mout_phyclk_usbhost20_phyclk_user_p, + MUX_SEL_FSYS1, 16, 1), + MUX(ID_NONE, "mout_phyclk_usbhost20_freeclk_user", + mout_phyclk_usbhost20_freeclk_user_p, + MUX_SEL_FSYS1, 12, 1), + MUX(ID_NONE, "mout_phyclk_usbhost20_clk48mohci_user", + mout_phyclk_usbhost20_clk48mohci_user_p, + MUX_SEL_FSYS1, 8, 1), + MUX(ID_NONE, "mout_phyclk_usbdrd30_pipe_pclk_user", + mout_phyclk_usbdrd30_pipe_pclk_user_p, + MUX_SEL_FSYS1, 4, 1), + MUX(ID_NONE, "mout_phyclk_usbdrd30_phyclock_user", + mout_phyclk_usbdrd30_phyclock_user_p, + MUX_SEL_FSYS1, 0, 1), +}; + +/* + * List of Mux clocks for CMU_G2D +*/ +struct samsung_mux_clock exynos5260_g2d_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_g2d_333_user", mout_aclk_g2d_333_user_p, + MUX_SEL_G2D, 0, 1), +}; + +/* + * List of Mux clocks for CMU_G3D +*/ +struct samsung_mux_clock exynos5260_g3d_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_g3d_pll", mout_g3d_pll_p, MUX_SEL_G3D, 0, 1), +}; + +/* + * List of Mux clocks for CMU_GSCL +*/ +struct samsung_mux_clock exynos5260_gscl_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_csis", mout_aclk_csis_p, MUX_SEL_GSCL, 24, 1), + MUX(ID_NONE, "mout_aclk_gscl_fimc_user", mout_aclk_gscl_fimc_user_p, + MUX_SEL_GSCL, 8, 1), + MUX(ID_NONE, "mout_aclk_m2m_400_user", mout_aclk_m2m_400_user_p, + MUX_SEL_GSCL, 4, 1), + MUX(ID_NONE, "mout_aclk_gscl_333_user", mout_aclk_gscl_333_user_p, + MUX_SEL_GSCL, 0, 1), +}; + +/* + * List of Mux clocks for CMU_ISP +*/ +struct samsung_mux_clock exynos5260_isp_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_isp_400_user", mout_isp_400_user_p, MUX_SEL_ISP0, + 4, 1), + MUX(ID_NONE, "mout_isp_266_user", mout_isp_266_user_p, MUX_SEL_ISP0, + 0, 1), +}; + +/* + * List of Mux clocks for CMU_KFC +*/ +struct samsung_mux_clock exynos5260_kfc_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_kfc_pll", mout_kfc_pll_p, MUX_SEL_KFC0, 0, 1), + MUX(ID_NONE, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), +}; + +/* + * List of Mux clocks for CMU_MFC +*/ +struct samsung_mux_clock exynos5260_mfc_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_mfc_333_user", mout_aclk_mfc_333_user_p, + MUX_SEL_MFC, 0, 1), +}; + +/* + * List of Mux clocks for CMU_MIF +*/ +struct samsung_mux_clock exynos5260_mif_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_clk2x_phy", mout_clk2x_phy_p, MUX_SEL_MIF, 24, 1), + MUX(ID_NONE, "mout_mif_drex2x", mout_mif_drex2x_p, MUX_SEL_MIF, 20, + 1), + MUX(ID_NONE, "mout_clkm_phy", mout_clkm_phy_p, MUX_SEL_MIF, 16, 1), + MUX(ID_NONE, "mout_mif_drex", mout_mif_drex_p, MUX_SEL_MIF, 12, 1), + MUX(ID_NONE, "mout_media_pll", mout_media_pll_p, MUX_SEL_MIF, 8, 1), + MUX(ID_NONE, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF, 4, 1), + MUX(ID_NONE, "mout_mem_pll", mout_mem_pll_p, MUX_SEL_MIF, 0, 1), +}; + +/* + * List of Mux clocks for CMU_PERI +*/ +struct samsung_mux_clock exynos5260_peri_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_spdif", mout_sclk_spdif_p, MUX_SEL_PERI1, 20, + 2), + MUX(ID_NONE, "mout_sclk_i2scod", mout_sclk_i2scod_p, MUX_SEL_PERI1, + 12, 2), + MUX(ID_NONE, "mout_sclk_pcm", mout_sclk_pcm_p, MUX_SEL_PERI1, 4, 2), +}; + +/* + * List of Mux clocks for CMU_TOP +*/ +struct samsung_mux_clock exynos5260_top_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_audtop_pll_user", mout_audtop_pll_user_p, + MUX_SEL_TOP_PLL0, 24, 1), + MUX(ID_NONE, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP_PLL0, 16, 1), + MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, + MUX_SEL_TOP_PLL0, 12, 1), + MUX(ID_NONE, "mout_bustop_pll_user", mout_bustop_pll_user_p, + MUX_SEL_TOP_PLL0, 8, 1), + MUX(ID_NONE, "mout_memtop_pll_user", mout_memtop_pll_user_p, + MUX_SEL_TOP_PLL0, 4, 1), + MUX(ID_NONE, "mout_mediatop_pll_user", mout_mediatop_pll_user_p, + MUX_SEL_TOP_PLL0, 0, 1), + + + MUX(ID_NONE, "mout_disp_disp_333", mout_disp_disp_333_p, + MUX_SEL_TOP_DISP0, 0, 1), + MUX(ID_NONE, "mout_aclk_disp_333", mout_aclk_disp_333_p, + MUX_SEL_TOP_DISP0, 8, 1), + MUX(ID_NONE, "mout_disp_disp_222", mout_disp_disp_222_p, + MUX_SEL_TOP_DISP0, 12, 1), + MUX(ID_NONE, "mout_aclk_disp_222", mout_aclk_disp_222_p, + MUX_SEL_TOP_DISP0, 20, 1), + MUX(ID_NONE, "mout_disp_media_pixel", mout_disp_media_pixel_p, + MUX_SEL_TOP_DISP1, 8, 1), + MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p, + MUX_SEL_TOP_DISP1, 0, 1), + + MUX(ID_NONE, "mout_sclk_peri_spi0_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 8, 1), + MUX(ID_NONE, "mout_sclk_peri_spi1_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 4, 1), + MUX(ID_NONE, "mout_sclk_peri_spi2_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 0, 1), + MUX(ID_NONE, "mout_sclk_peri_uart0_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 20, 1), + MUX(ID_NONE, "mout_sclk_peri_uart2_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 16, 1), + MUX(ID_NONE, "mout_sclk_peri_uart1_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 12, 1), + + MUX(ID_NONE, "mout_bus4_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 28, 1), + MUX(ID_NONE, "mout_bus4_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 24, 1), + MUX(ID_NONE, "mout_bus3_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 20, 1), + MUX(ID_NONE, "mout_bus3_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 16, 1), + MUX(ID_NONE, "mout_bus2_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 12, 1), + MUX(ID_NONE, "mout_bus2_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 8, 1), + MUX(ID_NONE, "mout_bus1_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 4, 1), + MUX(ID_NONE, "mout_bus1_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 0, 1), + + MUX(ID_NONE, "mout_sclk_fsys_usb", mout_sclk_fsys_usb_p, + MUX_SEL_TOP_FSYS, 0, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, MUX_SEL_TOP_FSYS, + 20, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, MUX_SEL_TOP_FSYS, + 12, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, MUX_SEL_TOP_FSYS, + 4, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_b", + mout_sclk_fsys_mmc0_sdclkin_b_p, MUX_SEL_TOP_FSYS, + 24, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_b", + mout_sclk_fsys_mmc1_sdclkin_b_p, MUX_SEL_TOP_FSYS, + 16, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_b", + mout_sclk_fsys_mmc2_sdclkin_b_p, MUX_SEL_TOP_FSYS, + 8, 1), + + MUX(ID_NONE, "mout_aclk_isp1_266", mout_aclk_isp1_266_p, + MUX_SEL_TOP_ISP10, 20, 1), + MUX(ID_NONE, "mout_isp1_media_266", mout_isp1_media_266_p, + MUX_SEL_TOP_ISP10, 16, 1), + MUX(ID_NONE, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, + MUX_SEL_TOP_ISP10, 8 , 1), + MUX(ID_NONE, "mout_isp1_media_400", mout_isp1_media_400_p, + MUX_SEL_TOP_ISP10, 4, 1), + + MUX(ID_NONE, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p, + MUX_SEL_TOP_ISP11, 4, 1), + MUX(ID_NONE, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p, + MUX_SEL_TOP_ISP11, 8, 1), + MUX(ID_NONE, "mout_sclk_isp1_uart", mout_sclk_isp_uart_p, + MUX_SEL_TOP_ISP11, 12, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor2", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 24, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor1", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 20, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor0", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 16, 1), + + MUX(ID_NONE, "mout_aclk_mfc_333", mout_aclk_mfc_333_p, + MUX_SEL_TOP_MFC, 8, 1), + MUX(ID_NONE, "mout_mfc_bustop_333", mout_mfc_bustop_333_p, + MUX_SEL_TOP_MFC, 4, 1), + + MUX(ID_NONE, "mout_aclk_g2d_333", mout_aclk_g2d_333_p, + MUX_SEL_TOP_G2D, 8, 1), + MUX(ID_NONE, "mout_g2d_bustop_333", mout_g2d_bustop_333_p, + MUX_SEL_TOP_G2D, 4, 1), + + MUX(ID_NONE, "mout_aclk_gscl_fimc", mout_aclk_gscl_fimc_p, + MUX_SEL_TOP_GSCL, 20, 1), + MUX(ID_NONE, "mout_gscl_bustop_fimc", mout_gscl_bustop_fimc_p, + MUX_SEL_TOP_GSCL, 16, 1), + MUX(ID_NONE, "mout_aclk_gscl_333", mout_aclk_gscl_333_p, + MUX_SEL_TOP_GSCL, 12, 1), + MUX(ID_NONE, "mout_gscl_bustop_333", mout_gscl_bustop_333_p, + MUX_SEL_TOP_GSCL, 8, 1), + MUX(ID_NONE, "mout_aclk_gscl_400", mout_aclk_gscl_400_p, + MUX_SEL_TOP_GSCL, 4, 1), + MUX(ID_NONE, "mout_m2m_mediatop_400", mout_m2m_mediatop_400_p, + MUX_SEL_TOP_GSCL, 0, 1), + + /* + * TODO: Add for ISP clocks + */ +}; + +/* DIVIDER CLOCKS */ + +/* + * List of Divider clocks for CMU_AUD +*/ +struct samsung_div_clock exynos5260_aud_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_aud_131", "mout_aud_pll_user", DIV_AUD0, 0, + 4), + DIV(ID_NONE, "dout_sclk_aud_uart", "mout_aud_pll_user", DIV_AUD1, 12, + 4), + DIV(ID_NONE, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm", DIV_AUD1, 4, + 8), + DIV(ID_NONE, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s", DIV_AUD1, 0, + 4), +}; + +/* + * List of Divider clocks for CMU_DISP +*/ +struct samsung_div_clock exynos5260_disp_div_clks[] __initdata = { + DIV(ID_NONE, "dout_sclk_hdmi_phy_pixel_clki", "mout_sclk_hdmi_pixel", + DIV_DISP, 16, 4), + DIV(ID_NONE, "dout_sclk_fimd1_extclkpll", "mout_sclk_disp_pixel_user", + DIV_DISP, 12, 4), + DIV(ID_NONE, "dout_pclk_disp_111", "mout_aclk_disp_222_user", + DIV_DISP, 8, 4), +}; + +/* + * List of Divider clocks for CMU_EGL +*/ +struct samsung_div_clock exynos5260_egl_div_clks[] __initdata = { + DIV(ID_NONE, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), + DIV(ID_NONE, "dout_egl_pclk_dbg", "dout_egl_atclk", DIV_EGL, 20, 3), + DIV(ID_NONE, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3), + DIV(ID_NONE, "dout_pclk_egl", "dout_egl_atclk", DIV_EGL, 12, 3), + DIV(ID_NONE, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), + DIV(ID_NONE, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), + DIV(ID_NONE, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), +}; + +/* + * List of Divider clocks for CMU_G2D +*/ +struct samsung_div_clock exynos5260_g2d_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", DIV_G2D, 0, + 3), +}; + +/* + * List of Divider clocks for CMU_G3D +*/ + +struct samsung_div_clock exynos5260_g3d_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), + DIV(ID_NONE, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), +}; + +/* + * List of Divider clocks for CMU_GSCL +*/ +struct samsung_div_clock exynos5260_gscl_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_csis_200", "mout_aclk_m2m_400_user", DIV_GSCL, + 4, 3), + DIV(ID_NONE, "dout_pclk_m2m_100", "mout_aclk_m2m_400_user", DIV_GSCL, + 0, 3), +}; + +/* + * List of Divider clocks for CMU_ISP +*/ + +struct samsung_div_clock exynos5260_isp_div_clks[] __initdata = { + DIV(ID_NONE, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), + DIV(ID_NONE, "dout_ca5_pclkdbg", "mout_kfc", DIV_ISP, 16, 4), + DIV(ID_NONE, "dout_ca5_atclkin", "mout_kfc", DIV_ISP, 12, 3), + DIV(ID_NONE, "dout_pclk_isp_133", "mout_kfc", DIV_ISP, 4, 4), + DIV(ID_NONE, "dout_pclk_isp_66", "mout_kfc", DIV_ISP, 0, 3), +}; + +/* + * List of Divider clocks for CMU_KFC +*/ +struct samsung_div_clock exynos5260_kfc_div_clks[] __initdata = { + DIV(ID_NONE, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), + DIV(ID_NONE, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3), + DIV(ID_NONE, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3), + DIV(ID_NONE, "dout_kfc_pclk_dbg", "dout_kfc2", DIV_KFC, 12, 3), + DIV(ID_NONE, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), + DIV(ID_NONE, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), + DIV(ID_NONE, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), +}; + +/* + * List of Divider clocks for CMU_MFC +*/ +struct samsung_div_clock exynos5260_mfc_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", DIV_MFC, 0, + 3), +}; + +/* + * List of Divider clocks for CMU_MIF +*/ +struct samsung_div_clock exynos5260_mif_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_bus_100", "dout_bus_pll", DIV_MIF, 28, 4), + DIV(ID_NONE, "dout_aclk_bus_200", "dout_bus_pll", DIV_MIF, 24, 3), + DIV(ID_NONE, "dout_aclk_mif_466", "dout_clk2x_phy", DIV_MIF, 20, 3), + DIV(ID_NONE, "dout_clk2x_phy", "mout_clk2x_phy", DIV_MIF, 16, 4), + DIV(ID_NONE, "dout_clkm_phy", "mout_clkm_phy", DIV_MIF, 12, 3), + DIV(ID_NONE, "dout_bus_pll", "mout_bus_pll", DIV_MIF, 8, 3), + DIV(ID_NONE, "dout_mem_pll", "mout_mem_pll", DIV_MIF, 4, 3), + DIV(ID_NONE, "dout_media_pll", "mout_media_pll", DIV_MIF, 0, 3), +}; + +/* + * List of Divider clocks for CMU_peri +*/ +struct samsung_div_clock exynos5260_peri_div_clks[] __initdata = { + DIV(ID_NONE, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 0, 6), + DIV(ID_NONE, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), +}; + +/* + * List of Divider clocks for CMU_TOP +*/ +struct samsung_div_clock exynos5260_top_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_mfc_333", "mout_aclk_mfc_333", + DIV_TOP_G2D_MFC, 4, 3), + + DIV(ID_NONE, "dout_aclk_g2d_333", "mout_aclk_g2d_333", + DIV_TOP_GSCL_ISP0, 0, 3), + + DIV(ID_NONE, "dout_sclk_isp1_sensor2_a", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 24, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor1_a", "mout_aclk_gscl_400", + DIV_TOP_GSCL_ISP0, 20, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor0_a", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 16, 4), + DIV(ID_NONE, "dout_aclk_gscl_fimc", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 8, 3), + DIV(ID_NONE, "dout_aclk_gscl_400", "mout_aclk_gscl_400", + DIV_TOP_GSCL_ISP0, 4, 3), + DIV(ID_NONE, "dout_aclk_gscl_333", "mout_aclk_gscl_333", + DIV_TOP_GSCL_ISP0, 0, 3), + + DIV(ID_NONE, "dout_sclk_isp1_spi0_b", "dout_sclk_isp1_spi0_a", + DIV_TOP_ISP10, 16, 8), + DIV(ID_NONE, "dout_sclk_isp1_spi0_a", "mout_sclk_isp1_spi0", + DIV_TOP_ISP10, 12, 4), + DIV(ID_NONE, "dout_aclk_isp1_400", "mout_aclk_isp1_400", + DIV_TOP_ISP10, 4, 3), + DIV(ID_NONE, "dout_aclk_isp1_266", "mout_aclk_isp1_266", + DIV_TOP_ISP10, 0, 3), + DIV(ID_NONE, "dout_sclk_isp1_uart", "mout_sclk_isp1_uart", + DIV_TOP_ISP11, 12, 4), + DIV(ID_NONE, "dout_sclk_isp1_spi1_b", "dout_sclk_isp1_spi1_a", + DIV_TOP_ISP11, 4, 8), + DIV(ID_NONE, "dout_sclk_isp1_spi1_a", "mout_sclk_isp1_spi1", + DIV_TOP_ISP11, 0, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor2_b", "dout_sclk_isp1_sensor2_a", + DIV_TOP_ISP11, 24, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor1_b", "dout_sclk_isp1_sensor1_a", + DIV_TOP_ISP11, 20, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor0_b", "dout_sclk_isp1_sensor0_a", + DIV_TOP_ISP11, 16, 4), + + DIV(ID_NONE, "dout_sclk_hpm_targetclk", "mout_bustop_pll_user", + DIV_TOP_HPM, 0, 3), + + DIV(ID_NONE, "dout_sclk_disp_pixel", "mout_sclk_disp_pixel", + DIV_TOP_DISP, 8, 3), + DIV(ID_NONE, "dout_aclk_disp_222", "mout_aclk_disp_222", DIV_TOP_DISP, + 4, 3), + DIV(ID_NONE, "dout_aclk_disp_333", "mout_aclk_disp_333", DIV_TOP_DISP, + 0, 3), + + DIV(ID_NONE, "dout_aclk_bus4_100", "mout_bus4_bustop_100", + DIV_TOP_BUS, 28, 4), + DIV(ID_NONE, "dout_aclk_bus4_400", "mout_bus4_bustop_400", + DIV_TOP_BUS, 24, 3), + DIV(ID_NONE, "dout_aclk_bus3_100", "mout_bus3_bustop_100", + DIV_TOP_BUS, 20, 4), + DIV(ID_NONE, "dout_aclk_bus3_400", "mout_bus3_bustop_400", + DIV_TOP_BUS, 16, 3), + DIV(ID_NONE, "dout_aclk_bus2_100", "mout_bus2_bustop_100", + DIV_TOP_BUS, 12, 4), + DIV(ID_NONE, "dout_aclk_bus2_400", "mout_bus2_bustop_400", + DIV_TOP_BUS, 8, 3), + DIV(ID_NONE, "dout_aclk_bus1_100", "mout_bus1_bustop_100", + DIV_TOP_BUS, 4, 4), + DIV(ID_NONE, "dout_aclk_bus1_400", "mout_bus1_bustop_400", + DIV_TOP_BUS, 0, 3), + + DIV(ID_NONE, "dout_sclk_peri_spi1_b", "dout_sclk_peri_spi1_a", + DIV_TOP_PERI0, 20, 8), + DIV(ID_NONE, "dout_sclk_peri_spi1_a", "mout_sclk_peri_spi1_clk", + DIV_TOP_PERI0, 16, 4), + DIV(ID_NONE, "dout_sclk_peri_spi0_b", "dout_sclk_peri_spi0_a", + DIV_TOP_PERI0, 8, 8), + DIV(ID_NONE, "dout_sclk_peri_spi0_a", "mout_sclk_peri_spi0_clk", + DIV_TOP_PERI0, 4, 4), + DIV(ID_NONE, "dout_sclk_peri_uart0", "mout_sclk_peri_uart0_uclk", + DIV_TOP_PERI1, 24, 4), + DIV(ID_NONE, "dout_sclk_peri_uart2", "mout_sclk_peri_uart2_uclk", + DIV_TOP_PERI1, 20, 4), + DIV(ID_NONE, "dout_sclk_peri_uart1", "mout_sclk_peri_uart1_uclk", + DIV_TOP_PERI1, 16, 4), + DIV(ID_NONE, "dout_sclk_peri_spi2_b", "dout_sclk_peri_spi2_a", + DIV_TOP_PERI1, 4, 8), + DIV(ID_NONE, "dout_sclk_peri_spi2_a", "mout_sclk_peri_spi2_clk", + DIV_TOP_PERI1, 0, 4), + DIV(ID_NONE, "dout_aclk_peri_aud", "mout_audtop_pll_user", + DIV_TOP_PERI2, 24, 3), + DIV(ID_NONE, "dout_aclk_peri_66", "mout_bustop_pll_user", + DIV_TOP_PERI2, 20, 4), + + DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_b", + "dout_sclk_fsys_mmc0_sdclkin_a", DIV_TOP_FSYS0, + 16, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_a", + "mout_sclk_fsys_mmc0_sdclkin_b", DIV_TOP_FSYS0, + 12, 4), + DIV(ID_NONE, "dout_sclk_fsys_usbdrd30_suspend_clk", + "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4), + DIV(ID_NONE, "dout_aclk_fsys_200", "mout_bustop_pll_user", + DIV_TOP_FSYS0, 0, 3), + + DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_b", + "dout_sclk_fsys_mmc2_sdclkin_a", DIV_TOP_FSYS1, + 16, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_a", + "mout_sclk_fsys_mmc2_sdclkin_b", DIV_TOP_FSYS1, + 12, 4), + DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_b", + "dout_sclk_fsys_mmc1_sdclkin_a", DIV_TOP_FSYS1, 4, + 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_a", + "mout_sclk_fsys_mmc1_sdclkin_b", DIV_TOP_FSYS1, 0, + 4), +}; + +/* GATE CLOCKS */ + +/* + * List of Gate clocks for CMU_AUD +*/ +struct samsung_gate_clock exynos5260_aud_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_axids_lpassp", "dout_aclk_aud_131", EN_ACLK_AUD, + 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axi2apb_lpassp", "dout_aclk_aud_131", EN_ACLK_AUD, + 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_lpassx", "dout_aclk_aud_131", EN_ACLK_AUD, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_audnd_133", "dout_aclk_aud_131", EN_ACLK_AUD, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_audnp_133", "dout_aclk_aud_131", EN_ACLK_AUD, 2, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_ACLK_SRAMC, "aclk_sramc", "dout_aclk_aud_131", EN_ACLK_AUD, + 1, CLK_IGNORE_UNUSED, 0), + GATE(AUD_ACLK_DMAC, "aclk_dmac", "dout_aclk_aud_131", EN_ACLK_AUD, 0, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_gpio_aud", "dout_aclk_aud_131", EN_PCLK_AUD, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_aud", "dout_aclk_aud_131", EN_PCLK_AUD, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_aud", "dout_aclk_aud_131", EN_PCLK_AUD, 5, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_AUD_UART, "pclk_aud_uart", "dout_aclk_aud_131", + EN_PCLK_AUD, 4, CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_PCM, "pclk_pcm", "dout_aclk_aud_131", EN_PCLK_AUD, 3, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_I2S, "pclk_i2s", "dout_aclk_aud_131", EN_PCLK_AUD, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sfr_ctrl", "dout_aclk_aud_131", EN_PCLK_AUD, 1, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_PCLK_DMAC, "pclk_dmac", "dout_aclk_aud_131", EN_PCLK_AUD, 0, + CLK_IGNORE_UNUSED, 0), + GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", + EN_SCLK_AUD, 2, CLK_IGNORE_UNUSED, 0), + GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", EN_SCLK_AUD, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_aud_i2s", "dout_sclk_aud_i2s", EN_SCLK_AUD, 0, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_DISP +*/ +struct samsung_gate_clock exynos5260_disp_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_noc_d_disp_disp1nd_333", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 30, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_disp_disp0nd_333", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 29, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius64to128_gsclkx_fimd1x", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 28, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius64to128_tv", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 27, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fimd0x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 26, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaxi_tv_aclkm", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 25, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaxi_tv_aclks", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_fimd0x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 23, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_tvx", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_tvx", "mout_aclk_disp_222_user", EN_ACLK_DISP, + 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fimd1x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 20, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_fimd1m1", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_fimd1m0", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_tvm1", "mout_aclk_disp_222_user", EN_ACLK_DISP, + 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_tvm0", "mout_aclk_disp_222_user", EN_ACLK_DISP, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_fimd1m1", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_fimd1m0", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_tvx", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_fimd1x", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer1_aclks", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer1_aclkm", + "mout_aclk_disp_222_user", EN_ACLK_DISP, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer0_aclks", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncfifo_mixer0_aclkm", + "mout_aclk_disp_222_user", EN_ACLK_DISP, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncdisp_m1", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncdisp_m0", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 4, CLK_IGNORE_UNUSED, 0), + GATE(DISP_ACLK_MIXER, "aclk_mixer", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 3, CLK_IGNORE_UNUSED, 0), + GATE(DISP_ACLK_HDMI, "aclk_hdmi_link", "mout_aclk_disp_222_user", + EN_ACLK_DISP, 2, CLK_IGNORE_UNUSED, 0), + GATE(DISP_ACLK_FIMD1, "aclk_fimd1_128", "mout_aclk_disp_333_user", + EN_ACLK_DISP, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaxim_gsclx_fimd1x", + "mout_aclk_disp_333_user", EN_ACLK_DISP, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "phyclk_dptx_link_i_div2", + "mout_phyclk_dptx_phy_clk_div2_user", + EN_SCLK_DISP0, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch3_tx", + "mout_phyclk_dptx_phy_ch3_txd_clk_user", + EN_SCLK_DISP0, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch2_tx", + "mout_phyclk_dptx_phy_ch2_txd_clk_user", + EN_SCLK_DISP0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch1_tx", + "mout_phyclk_dptx_phy_ch1_txd_clk_user", + EN_SCLK_DISP0, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_ch0_tx", + "mout_phyclk_dptx_phy_ch0_txd_clk_user", + EN_SCLK_DISP0, 1, + CLK_IGNORE_UNUSED, 0), + GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki", + "dout_sclk_hdmi_phy_pixel_clki", EN_SCLK_DISP0, + 29, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "pclk_ppmu_fimd0x", "dout_pclk_disp_111", EN_PCLK_DISP, + 30, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_noc_p_disp_dispnp_111", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 28, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncaxi_tv", "dout_pclk_disp_111", EN_PCLK_DISP, + 27, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_disp", "dout_pclk_disp_111", EN_PCLK_DISP, + 26, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_SMMU_TV, "pclk_smmu3_tvx", "dout_pclk_disp_111", + EN_PCLK_DISP, 25, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_SMMU_FIMD1M1, "pclk_smmu3_fimd1m1", + "dout_pclk_disp_111", EN_PCLK_DISP, 23, + CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_SMMU_FIMD1M0, "pclk_smmu3_fimd1m0", + "dout_pclk_disp_111", EN_PCLK_DISP, 22, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_tvm1", "dout_pclk_disp_111", EN_PCLK_DISP, 21, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_tvm0", "dout_pclk_disp_111", EN_PCLK_DISP, 20, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_fimd1m1", "dout_pclk_disp_111", EN_PCLK_DISP, + 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_fimd1m0", "dout_pclk_disp_111", EN_PCLK_DISP, + 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_tvx", "dout_pclk_disp_111", EN_PCLK_DISP, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_fimd1x", "dout_pclk_disp_111", EN_PCLK_DISP, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_disp", "dout_pclk_disp_111", EN_PCLK_DISP, 14, + CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_HDMIPHY, "pclk_hdmi_phy_i", "dout_pclk_disp_111", + EN_PCLK_DISP, 13, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_HDMI, "pclk_hdmi_link", "dout_pclk_disp_111", + EN_PCLK_DISP, 12, CLK_IGNORE_UNUSED, 0), + GATE(DISP_PCLK_DSIM1, "pclk_dsim1", "dout_pclk_disp_111", + EN_PCLK_DISP, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_dptx_link_i_pclk1", "dout_pclk_disp_111", + EN_PCLK_DISP, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_dptx_link_i_pclk0", "dout_pclk_disp_111", + EN_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncaxim_gsclx_fimd1x", "dout_pclk_disp_111", + EN_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ahb2apb_disp1p", "dout_pclk_disp_111", + EN_PCLK_DISP, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ahb2apb_disp0p", "dout_pclk_disp_111", + EN_PCLK_DISP, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahbsyncdn_disp0p", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahbsyncdn_disp1p", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_noc_p_dispnp_111", "mout_aclk_disp_333_user", + EN_PCLK_DISP, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_fimd1_128", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_sfrdisph", "mout_aclk_disp_222_user", + EN_PCLK_DISP, 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_fimd1_128_extclkpll", "dout_sclk_fimd1_extclkpll", + EN_SCLK_DISP0, 31, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_hdmi_link_i_spdif", "mout_sclk_hdmi_spdif", + EN_SCLK_DISP0, 27, CLK_IGNORE_UNUSED, 0), + GATE(DISP_SCLK_HDMI, "sclk_hdmi_link_i_pixel", + "mout_phyclk_hdmi_phy_pixel_clko_user", + EN_SCLK_DISP0, 26, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_hdmi_phy_tmds_clki", + "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + EN_SCLK_DISP0, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_hdmi_phy_ref_cko", + "mout_phyclk_hdmi_phy_ref_clko_user", + EN_SCLK_DISP0, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_hdmi_link_i_tmds", + "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + EN_SCLK_DISP0, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dsim1_rxclkesc0", + "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", + EN_SCLK_DISP0, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dsim1_bitclkdiv8", + "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", + EN_SCLK_DISP0, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_dptx_link_i_24m", + "mout_phyclk_dptx_phy_o_ref_clk_24m_user", + EN_SCLK_DISP0, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mixer_i_vclk_hdmi", + "mout_phyclk_hdmi_phy_pixel_clko_user", + EN_SCLK_DISP1, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkescclk", + "mout_sclk_dsim1_tx_clk_esc_clk_user", + EN_SCLK_DISP1, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc3", + "mout_sclk_dsim1_tx_clk_esc3_user", EN_SCLK_DISP1, + 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc2", + "mout_sclk_dsim1_tx_clk_esc2_user", EN_SCLK_DISP1, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc1", + "mout_sclk_dsim1_tx_clk_esc1_user", EN_SCLK_DISP1, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_mipi_dphy_4l_m_txclkesc0", + "mout_sclk_dsim1_tx_clk_esc0_user", EN_SCLK_DISP1, + 0, CLK_IGNORE_UNUSED, 0), + + GATE(DISP_DP, "dptx_phy", "fin_pll", EN_IP_DISP, 5, CLK_IGNORE_UNUSED, + 0), +}; + +/* + * List of Gate clocks for CMU_EGL +*/ +struct samsung_gate_clock exynos5260_egl_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_cssys_traceclkin", "dout_egl_atclk", EN_ACLK_EGL, + 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_cssys_ctm", "dout_egl_atclk", EN_ACLK_EGL, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_cssys", "dout_egl_atclk", EN_ACLK_EGL, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_cssys_atclk", "dout_egl_atclk", EN_ACLK_EGL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_3_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_2_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_1_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asatbmat_kfc_0_cssys", "dout_egl_atclk", + EN_ACLK_EGL, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbs_cssys_cci", "dout_egl_atclk", + EN_ACLK_EGL, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ace_async_egl_cci_i", "dout_aclk_egl", + EN_ACLK_EGL, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_eglp", "dout_pclk_egl", EN_ACLK_EGL, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_eagle_200", "dout_pclk_egl", EN_ACLK_EGL, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_egl_hpm_sfrif", "dout_pclk_egl", EN_PCLK_EGL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_cssys_pclkdbg", "dout_egl_pclk_dbg", EN_PCLK_EGL, + 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_cortexa15_pclkdbg", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_aud_cssys", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_isp_cssys", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_kfc_cssys", "dout_egl_pclk_dbg", + EN_PCLK_EGL, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_egl", "dout_pclk_egl", EN_PCLK_EGL, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_egl", "dout_pclk_egl", EN_PCLK_EGL, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_secjtag", "dout_egl_pclk_dbg", EN_PCLK_EGL, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_iem_hpm_target", "dout_sclk_hpm_targetclk", + EN_SCLK_EGL, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_FSYS +*/ +struct samsung_gate_clock exynos5260_fsys_gate_clks[] __initdata = { + GATE(FSYS_HCLK_TSI, "hclk_tsi", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 25, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_PCLK_GPIO, "pclk_gpio", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_usblink", "dout_aclk_fsys_200", EN_ACLK_FSYS, 23, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_fsys", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_fsys_top", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu", "dout_aclk_fsys_200", EN_ACLK_FSYS, 20, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_USBHOST20, "hclk_usbhost20", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 19, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_SROMC, "hclk_sromc", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 18, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_MMC2, "hclk_mmc2", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 17, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_MMC1, "hclk_mmc1", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 16, CLK_IGNORE_UNUSED, 0), + GATE(FSYS_HCLK_MMC0, "hclk_mmc0", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_fsysp", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_usbhs", "dout_aclk_fsys_200", EN_ACLK_FSYS, + 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_fsysh", "dout_aclk_fsys_200", EN_ACLK_FSYS, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fd64x", "dout_aclk_fsys_200", EN_ACLK_FSYS, 8, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_ACLK_USBDRD30, "aclk_usbdrd30", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu", "dout_aclk_fsys_200", EN_ACLK_FSYS, 6, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_ACLK_PDMA0, "aclk_pdma0", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_fsys_200", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_fsys_200", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius32to64_usbhs_fd64x", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axius32to64_pdma0_fd64x", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ahb2axi_usbhs_fd64x", "dout_aclk_fsys_200", + EN_ACLK_FSYS, 0, CLK_IGNORE_UNUSED, 0), + + GATE(FSYS_ACLK_RTIC, "aclk_rtic_i", "dout_aclk_fsys_200", + EN_ACLK_FSYS_SECURE_RTIC, 12, CLK_IGNORE_UNUSED, + 0), + + GATE(FSYS_PCLK_SMMU_RTIC, "pclk_smmu_rtic", "dout_aclk_fsys_200", + EN_ACLK_FSYS_SECURE_SMMU_RTIC, 14, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_rtic", "dout_aclk_fsys_200", + EN_ACLK_FSYS_SECURE_SMMU_RTIC, 13, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "phyclk_usbdrd30_udrd30_pipe", + "mout_phyclk_usbdrd30_pipe_pclk_user", + EN_SCLK_FSYS, 8, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g", + "mout_phyclk_usbdrd30_phyclock_user", + EN_SCLK_FSYS, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_usbhost20_clk48mohci", + "mout_phyclk_usbhost20_clk48mohci_user", + EN_SCLK_FSYS, 6, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", + "mout_phyclk_usbdrd30_phyclock_user", + EN_SCLK_FSYS, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "phyclk_usbhost20_freeclock_gatet", + "mout_phyclk_usbhost20_freeclk_user", + EN_SCLK_FSYS, 0, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_G2D +*/ +struct samsung_gate_clock exynos5260_g2d_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_xiu_async_g2d2x_g2d1x_aclks", + "mout_aclk_g2d_333_user", EN_ACLK_G2D, 26, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_async_g2d2x_g2d1x_aclkm", + "mout_aclk_g2d_333_user", EN_ACLK_G2D, 25, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mdma", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_g2d2x", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 23, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_g2d1x", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_jpeg", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 20, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_jpeg", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, + 10, CLK_IGNORE_UNUSED, 0), + GATE(G2D_ACLK_MDMA, "aclk_mdma", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_jpeg", "mout_aclk_g2d_333_user", EN_ACLK_G2D, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_g2d", "mout_aclk_g2d_333_user", EN_ACLK_G2D, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_slim_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_mdma", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_jpeg", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axuser_sel_g2d", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axi_us_64to128_g2d2x_g2d1x", + "mout_aclk_g2d_333_user", EN_ACLK_G2D, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_alb_g2d1x_g2dnd", "mout_aclk_g2d_333_user", + EN_ACLK_G2D, 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SSS, 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_slim_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SLIM_SSS, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_slim_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 17, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_sss", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_SSS, 18, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu_mdma", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_MDMA, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_g2d", "mout_aclk_g2d_333_user", + EN_ACLK_G2D_SECURE_SMMU_G2D, 19, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "hclk_ahb_tz", "dout_pclk_g2d_83", EN_PCLK_G2D, 18, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_xiu_async_g2d2x_g2d1x", "dout_pclk_g2d_83", + EN_PCLK_G2D, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mdma", "dout_pclk_g2d_83", EN_PCLK_G2D, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 14, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_jpeg", "dout_pclk_g2d_83", EN_PCLK_G2D, 13, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_jpeg", "dout_pclk_g2d_83", EN_PCLK_G2D, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_alb_g2d1x_g2dnd", "dout_pclk_g2d_83", EN_PCLK_G2D, + 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbslave_g2dh_jpeg", "dout_pclk_g2d_83", + EN_PCLK_G2D, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbmaster_g2dh_jpeg", + "mout_aclk_g2d_333_user", EN_PCLK_G2D, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_sfrg2d", "dout_pclk_g2d_83", EN_PCLK_G2D, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_g2d", "dout_pclk_g2d_83", EN_PCLK_G2D, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_smmu_slim_sss", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu_sss", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_SSS, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu_mdma", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_MDMA, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_g2d", "dout_pclk_g2d_83", + EN_PCLK_G2D_SECURE_SMMU_G2D, 12, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_G3D +*/ +struct samsung_gate_clock exynos5260_g3d_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_noc_p_g3d", "dout_pclk_g3d", EN_ACLK_G3D, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncapb_socp_g3d", "dout_aclk_g3d", EN_ACLK_G3D, + 3, CLK_IGNORE_UNUSED, 0), + GATE(G3D_ACLK_G3D, "aclk_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_acr_lite_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_g3d", "dout_aclk_g3d", EN_ACLK_G3D, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_g3d_hpm_sfrif", "dout_pclk_g3d", EN_PCLK_G3D, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_reg_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_ace_lite_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_socp_g3d", "dout_pclk_g3d", EN_PCLK_G3D, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_g3d", "dout_pclk_g3d", EN_PCLK_G3D, 0, + CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_GSCL +*/ +struct samsung_gate_clock exynos5260_gscl_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_noc_d_gscl_333", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 27, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_mscl_400", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 26, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_gscl_100", "dout_pclk_m2m_100", + EN_ACLK_GSCL, 25, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_msclx", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 24, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_gsclx", "mout_aclk_gscl_333", EN_ACLK_GSCL, + 23, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mscl1", "mout_aclk_m2m_400_user", EN_ACLK_GSCL, + 19, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mscl0", "mout_aclk_m2m_400_user", EN_ACLK_GSCL, + 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_mscl", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_m2mscaler1", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_m2mscaler0", "mout_aclk_m2m_400_user", + EN_ACLK_GSCL, 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_asyncs_gsclx", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_gscl1", "mout_aclk_gscl_333", EN_ACLK_GSCL, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_gscl0", "mout_aclk_gscl_333", EN_ACLK_GSCL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_gscl", "mout_aclk_gscl_333", EN_ACLK_GSCL, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncs_gscl1", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncs_gscl0", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_pixelasyncm_gscl0", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 3, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_ACLK_GSCL1, "aclk_gscaler1", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 1, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_ACLK_GSCL0, "aclk_gscaler0", "mout_aclk_gscl_333", + EN_ACLK_GSCL, 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_noc_d_fimc_333", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_fimc_lite_d_i", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_fimc_lite_b_i", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_fimc_lite_a_i", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_lite_d", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_lite_b", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_lite_a", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_lite_d", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_lite_b", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_lite_a", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_fimc", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_xiu_fimcx", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_FIMC, 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_gscl0", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_gscl1", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_mscl0", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 00, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_smmu3_mscl1", "mout_aclk_gscl_fimc_user", + EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 21, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_sysreg_gscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, + 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mscl1", "dout_pclk_m2m_100", EN_PCLK_GSCL, 13, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mscl0", "dout_pclk_m2m_100", EN_PCLK_GSCL, 12, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_gscl1", "dout_pclk_m2m_100", EN_PCLK_GSCL, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_gscl0", "dout_pclk_m2m_100", EN_PCLK_GSCL, 10, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_mscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_gscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_gscl", "dout_pclk_m2m_100", EN_PCLK_GSCL, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_m2mscaler1", "dout_pclk_m2m_100", EN_PCLK_GSCL, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_m2mscaler0", "dout_pclk_m2m_100", EN_PCLK_GSCL, 5, + CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_GSCL1, "pclk_gscaler1", "dout_pclk_m2m_100", + EN_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_GSCL0, "pclk_gscaler0", "dout_pclk_m2m_100", + EN_PCLK_GSCL, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_msclp", "dout_pclk_m2m_100", EN_PCLK_GSCL, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_gsclp", "dout_pclk_m2m_100", EN_PCLK_GSCL, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_fimc", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_lite_d", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_lite_b", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_lite_a", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_lite_d", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_lite_b", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_lite_a", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_fimc_lite_d", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_fimc_lite_b", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_fimc_lite_a", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_csis1", "dout_pclk_m2m_100", EN_PCLK_GSCL_FIMC, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_csis0", "dout_pclk_m2m_100", EN_PCLK_GSCL_FIMC, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_hpm9t_wrap_gscl", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_fimcp", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb_gsclh", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbm_isph", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbm_fimcnp", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_asyncahbs_fimcnp", "dout_pclk_m2m_100", + EN_PCLK_GSCL_FIMC, 0, CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_SMMU_GSCL0, "pclk_smmu3_gscl0", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 14, + CLK_IGNORE_UNUSED, 0), + GATE(GSCL_PCLK_SMMU_GSCL1, "pclk_smmu3_gscl1", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_mscl0", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 16, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_smmu3_mscl1", "dout_pclk_m2m_100", + EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 17, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_gscl_hpm_targetclk", "dout_sclk_hpm_targetclk", + EN_SCLK_GSCL, 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_csis1_wrap", "dout_aclk_csis_200", + EN_SCLK_GSCL_FIMC, 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_csis0_wrap", "dout_aclk_csis_200", + EN_SCLK_GSCL_FIMC, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_ISP +*/ +struct samsung_gate_clock exynos5260_isp_gate_clks[] __initdata = { +}; + +/* + * List of Gate clocks for CMU_KFC +*/ +struct samsung_gate_clock exynos5260_kfc_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_asyncatbs_kfc_3", "dout_kfc_atclk", EN_ACLK_KFC, + 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncatbs_kfc_2", "dout_kfc_atclk", EN_ACLK_KFC, + 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncatbs_kfc_1", "dout_kfc_atclk", EN_ACLK_KFC, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncatbs_kfc_0", "dout_kfc_atclk", EN_ACLK_KFC, + 1, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncaces_kfc_cci", "dout_aclk_kfc", EN_ACLK_KFC, + 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_kfc_hpm_sfrif", "dout_pclk_kfc", EN_PCLK_KFC, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc3", "dout_aclk_kfc", + EN_PCLK_KFC, 8, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc2", "dout_aclk_kfc", + EN_PCLK_KFC, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc1", "dout_aclk_kfc", + EN_PCLK_KFC, 6, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_atbdownsizer63to32_kfc0", "dout_aclk_kfc", + EN_PCLK_KFC, 5, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_ahb2apb_kfcp", "dout_pclk_kfc", EN_PCLK_KFC, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_nocp_kfc_225", "dout_pclk_kfc", EN_PCLK_KFC, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_dapapbmux_dbg", "dout_kfc_pclk_dbg", EN_PCLK_KFC, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_kfc", "dout_pclk_kfc", EN_PCLK_KFC, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_kfc", "dout_pclk_kfc", EN_PCLK_KFC, 0, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_kfc_hpm_targetclk", "dout_sclk_hpm_targetclk", + EN_SCLK_KFC, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_MFC +*/ +struct samsung_gate_clock exynos5260_mfc_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_xiu_mfcx_2x1_top", "mout_aclk_mfc_333_user", + EN_ACLK_MFC, 7, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mfcm1", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 4, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_mfcm0", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_mfc", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_mfc_333", "mout_aclk_mfc_333_user", + EN_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), + GATE(MFC_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_333_user", EN_ACLK_MFC, + 0, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_smmu2_mfcm1", "mout_aclk_mfc_333_user", + EN_ACLK_SECURE_SMMU2_MFC, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "aclk_smmu2_mfcm0", "mout_aclk_mfc_333_user", + EN_ACLK_SECURE_SMMU2_MFC, 5, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "pclk_sysreg_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mfcm1", "dout_pclk_mfc_83", EN_PCLK_MFC, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_mfcm0", "dout_pclk_mfc_83", EN_PCLK_MFC, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 3, + CLK_IGNORE_UNUSED, 0), + GATE(MFC_PCLK_MFC, "pclk_mfc", "dout_pclk_mfc_83", EN_PCLK_MFC, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ahb2apb_mfcp", "dout_pclk_mfc_83", EN_PCLK_MFC, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mfc_83", "dout_pclk_mfc_83", EN_PCLK_MFC, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(MFC_PCLK_SMMU_MFC1, "pclk_smmu2_mfcm1", "dout_pclk_mfc_83", + EN_PCLK_SECURE_SMMU2_MFC, 8, CLK_IGNORE_UNUSED, 0), + GATE(MFC_PCLK_SMMU_MFC0, "pclk_smmu2_mfcm0", "dout_pclk_mfc_83", + EN_PCLK_SECURE_SMMU2_MFC, 8, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_MIF +*/ +struct samsung_gate_clock exynos5260_mif_gate_clks[] __initdata = { + GATE(ID_NONE, "aclk_lpddr3phy_wrap_u1", "dout_clk2x_phy", EN_ACLK_MIF, + 22, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_lpddr3phy_wrap_u0", "dout_clk2x_phy", EN_ACLK_MIF, + 21, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ace_async_mi_top_kfc", "dout_aclk_mif_466", + EN_ACLK_MIF, 20, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ace_async_mi_top_egl", "dout_aclk_mif_466", + EN_ACLK_MIF, 19, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_asyncahb_master_hclkm", "dout_aclk_mif_466", + EN_ACLK_MIF, 18, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ahb2axi_mmd32", "dout_aclk_mif_466", EN_ACLK_MIF, + 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_axi_us_32to128_top_buf", "dout_aclk_mif_466", + EN_ACLK_MIF, 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_kfc", "dout_aclk_mif_466", EN_ACLK_MIF, 15, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_qe_egl", "dout_aclk_mif_466", EN_ACLK_MIF, 14, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi1_1", "dout_aclk_mif_466", EN_ACLK_MIF, + 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi1_0", "dout_aclk_mif_466", EN_ACLK_MIF, + 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi0_1", "dout_aclk_mif_466", EN_ACLK_MIF, + 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_drexi0_0", "dout_aclk_mif_466", EN_ACLK_MIF, + 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_kfc", "dout_aclk_mif_466", EN_ACLK_MIF, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_ppmu_egl", "dout_aclk_mif_466", EN_ACLK_MIF, 8, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_d_mif", "dout_aclk_mif_466", EN_ACLK_MIF, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_cci400", "dout_aclk_mif_466", EN_ACLK_MIF, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mif_nocpnp_100", "dout_aclk_bus_100", + EN_ACLK_MIF, 3, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mif_nocdnp_200", "dout_aclk_bus_200", + EN_ACLK_MIF, 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "aclk_noc_p_mif_nocpnd_200", "dout_aclk_bus_200", + EN_ACLK_MIF, 1, CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "aclk_drexi_v2_u1", "dout_aclk_bus_200", + EN_ACLK_MIF_SECURE_DREX1_TZ, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "aclk_drexi_v2_u0", "dout_aclk_bus_200", + EN_ACLK_MIF_SECURE_DREX0_TZ, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "aclk_intmem", "dout_aclk_bus_200", + EN_ACLK_MIF_SECURE_INTMEM, 0, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "pclk_sysreg_mif", "dout_aclk_bus_100", EN_PCLK_MIF, 21, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pmu_mif", "dout_aclk_bus_100", EN_PCLK_MIF, 20, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_kfc", "dout_aclk_bus_100", EN_PCLK_MIF, 19, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_qe_egl", "dout_aclk_bus_100", EN_PCLK_MIF, 18, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex1_1", "dout_aclk_bus_100", EN_PCLK_MIF, + 17, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex1_0", "dout_aclk_bus_100", EN_PCLK_MIF, + 16, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex0_1", "dout_aclk_bus_100", EN_PCLK_MIF, + 15, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_drex0_0", "dout_aclk_bus_100", EN_PCLK_MIF, + 14, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_kfc", "dout_aclk_bus_100", EN_PCLK_MIF, 13, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_ppmu_egl", "dout_aclk_bus_100", EN_PCLK_MIF, 12, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_lpddr3phy_wrap_u1", "dout_aclk_bus_100", + EN_PCLK_MIF, 11, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_lpddr3phy_wrap_u0", "dout_aclk_bus_100", + EN_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sfr_apbif", "dout_aclk_bus_100", EN_PCLK_MIF, 7, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_gic_cpu", "dout_aclk_bus_100", EN_PCLK_MIF, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_axi2apb_csp", "dout_aclk_bus_100", EN_PCLK_MIF, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_axi2apb_cdrexp", "dout_aclk_bus_100", EN_PCLK_MIF, + 2, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_xiu_cnvsx", "dout_aclk_bus_100", EN_PCLK_MIF, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_asyncapb_cssys", "dout_aclk_bus_100", EN_PCLK_MIF, + 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_monocnt_apbif", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_MONOCNT, 5, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_rtc_apbif", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_RTC_APBIF, 6, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_drexi_v2_u1", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_DREX1_TZ, 0, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_drexi_v2_u0", "dout_aclk_bus_100", + EN_PCLK_MIF_SECURE_DREX0_TZ, 0, CLK_IGNORE_UNUSED, + 0), + + GATE(ID_NONE, "sclk_lpddr3phy_wrap_u1", "dout_clkm_phy", EN_SCLK_MIF, + 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_lpddr3phy_wrap_u0", "dout_clkm_phy", EN_SCLK_MIF, + 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_PERI +*/ +struct samsung_gate_clock exynos5260_peri_gate_clks[] __initdata = { + GATE(ID_NONE, "pclk_pmu_peri", "dout_aclk_peri_66", EN_PCLK_PERI0, 23, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2S1, "pclk_i2s1", "dout_aclk_peri_66", EN_PCLK_PERI0, + 22, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C7, "pclk_i2c7", "dout_aclk_peri_66", EN_PCLK_PERI0, + 20, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C6, "pclk_i2c6", "dout_aclk_peri_66", EN_PCLK_PERI0, + 19, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C5, "pclk_i2c5", "dout_aclk_peri_66", EN_PCLK_PERI0, + 18, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C4, "pclk_i2c4", "dout_aclk_peri_66", EN_PCLK_PERI0, + 17, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C9, "pclk_i2c9", "dout_aclk_peri_66", EN_PCLK_PERI0, + 16, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C8, "pclk_i2c8", "dout_aclk_peri_66", EN_PCLK_PERI0, + 15, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C11, "pclk_i2c11", "dout_aclk_peri_66", + EN_PCLK_PERI0, 14, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_I2C10, "pclk_i2c10", "dout_aclk_peri_66", + EN_PCLK_PERI0, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_hdmicec", "dout_aclk_peri_66", EN_PCLK_PERI0, 12, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_cmutop", "dout_aclk_peri_66", EN_PCLK_PERI0, 11, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_efuse_writer_sc", "dout_aclk_peri_66", + EN_PCLK_PERI0, 10, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_efuse_writer_nsc", "dout_aclk_peri_66", + EN_PCLK_PERI0, 9, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "nclk_perinp", "dout_aclk_peri_66", EN_PCLK_PERI0, 5, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peris1p", "dout_aclk_peri_66", EN_PCLK_PERI0, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peris0p", "dout_aclk_peri_66", EN_PCLK_PERI0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_perih", "dout_aclk_peri_66", EN_PCLK_PERI0, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peric1p", "dout_aclk_peri_66", EN_PCLK_PERI0, 1, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "hclk_peric0p", "dout_aclk_peri_66", EN_PCLK_PERI0, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "pclk_asv_tbl", "dout_aclk_peri_66", EN_PCLK_PERI1, 20, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_ADC, "pclk_adc", "dout_aclk_peri_66", EN_PCLK_PERI1, + 15, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_TMU1, "pclk_tmu1", "dout_aclk_peri_66", EN_PCLK_PERI1, + 14, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_TMU0, "pclk_tmu0", "dout_aclk_peri_66", EN_PCLK_PERI1, + 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_sysreg_peri", "dout_aclk_peri_66", EN_PCLK_PERI1, + 12, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPI2, "pclk_spi2", "dout_aclk_peri_66", EN_PCLK_PERI1, + 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPI1, "pclk_spi1", "dout_aclk_peri_66", EN_PCLK_PERI1, + 10, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPI0, "pclk_spi0", "dout_aclk_peri_66", EN_PCLK_PERI1, + 9, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_SPDIF, "pclk_spdif", "dout_aclk_peri_66", + EN_PCLK_PERI1, 8, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_PWM, "pclk_pwm", "dout_aclk_peri_66", EN_PCLK_PERI1, 5, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_ABB, "pclk_abb", "dout_aclk_peri_66", EN_PCLK_PERI1, 2, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_pcm1", "dout_aclk_peri_66", EN_PCLK_PERI1, 1, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_MCT, "pclk_mct", "dout_aclk_peri_66", EN_PCLK_PERI1, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(PERI_PCLK_HSIC3, "pclk_hsic3", "dout_aclk_peri_66", + EN_PCLK_PERI2, 17, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_HSIC2, "pclk_hsic2", "dout_aclk_peri_66", + EN_PCLK_PERI2, 15, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_HSIC1, "pclk_hsic1", "dout_aclk_peri_66", + EN_PCLK_PERI2, 13, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_HSIC0, "pclk_hsic0", "dout_aclk_peri_66", + EN_PCLK_PERI2, 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_UART0, "pclk_uart0", "dout_aclk_peri_66", + EN_PCLK_PERI2, 9, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_UART2, "pclk_uart2", "dout_aclk_peri_66", + EN_PCLK_PERI2, 8, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_UART1, "pclk_uart1", "dout_aclk_peri_66", + EN_PCLK_PERI2, 7, CLK_IGNORE_UNUSED, 0), + + GATE(PERI_PCLK_WDT_KFC, "pclk_wdt_kfc", "dout_aclk_peri_66", + EN_PCLK_PERI3, 20, CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_WDT_EGL, "pclk_wdt_egl", "dout_aclk_peri_66", + EN_PCLK_PERI3, 19, CLK_IGNORE_UNUSED, 0), + + GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2", + EN_SCLK_PERI, 12, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1", + EN_SCLK_PERI, 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0", + EN_SCLK_PERI, 10, CLK_IGNORE_UNUSED, 0), + + GATE(PERI_PCLK_CHIPID, "pclk_chipid", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_CHIPID, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_provkey0", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_PROVKEY0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_provkey1", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_PROVKEY1, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "pclk_seckey", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_SECKEY, 7, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_antirbkcnt", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_ANTIRBKCNT, 7, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_PCLK_TOP_RTC, "pclk_top_rtc", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TOP_RTC, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc3", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 19, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc2", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 18, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc1", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 17, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc0", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 16, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc10", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc9", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc8", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc7", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc6", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc5", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, + 0), + GATE(ID_NONE, "pclk_tzpc4", "dout_aclk_peri_66", + EN_PCLK_PERI_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, + 0), + + GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b", + EN_SCLK_PERI, 9, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b", + EN_SCLK_PERI, 8, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b", + EN_SCLK_PERI, 7, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b", + EN_SCLK_PERI, 2, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, + CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, + CLK_IGNORE_UNUSED, 0), + + GATE(PERI_SCLK_RTC, "sclk_rtc_clkout", "xrtcxti", + EN_SCLK_PERI_SECURE_TOP_RTC, 7, CLK_IGNORE_UNUSED, + 0), +}; + +/* + * List of Gate clocks for CMU_TOP +*/ +struct samsung_gate_clock exynos5260_top_gate_clks[] __initdata = { + GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel", + EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED, 0), + GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin", + "dout_sclk_fsys_mmc2_sdclkin_b", EN_SCLK_TOP, 9, + CLK_SET_RATE_PARENT, + 0), + GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin", + "dout_sclk_fsys_mmc1_sdclkin_b", EN_SCLK_TOP, 8, + CLK_SET_RATE_PARENT, + 0), + GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", + "dout_sclk_fsys_mmc0_sdclkin_b", EN_SCLK_TOP, 7, + CLK_SET_RATE_PARENT, + 0), +}; + +/* +* Applicable for all 2550 Type PLLS for Exynos5260, listed below +* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, +* BUS_PLL, MEDIA_PLL, G3D_PLL. +*/ +static const struct samsung_pll_rate_table exynos5260_pll2550_24mhz_tbl[] = { + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 400, 4, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(933000000, 311, 4, 1), + PLL_35XX_RATE(900000000, 300, 4, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(733000000, 733, 12, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(667000000, 667, 12, 1), + PLL_35XX_RATE(633000000, 211, 4, 1), + PLL_35XX_RATE(620000000, 310, 3, 2), + PLL_35XX_RATE(600000000, 400, 4, 2), + PLL_35XX_RATE(543000000, 362, 4, 2), + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(450000000, 300, 4, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + PLL_35XX_RATE(160000000, 160, 3, 3), +}; + +/* +* Applicable for 2650 Type PLL for AUD_PLL. +*/ +static const struct samsung_pll_rate_table exynos5260_pll2650_24mhz_tbl[] = { + PLL_36XX_RATE(1600000000, 200, 3, 0, 0), + PLL_36XX_RATE(1200000000, 100, 2, 0, 0), + PLL_36XX_RATE(1000000000, 250, 3, 1, 0), + PLL_36XX_RATE(800000000, 200, 3, 1, 0), + PLL_36XX_RATE(600000000, 100, 2, 1, 0), + PLL_36XX_RATE(532000000, 266, 3, 2, 0), + PLL_36XX_RATE(480000000, 160, 2, 2, 0), + PLL_36XX_RATE(432000000, 144, 2, 2, 0), + PLL_36XX_RATE(400000000, 200, 3, 2, 0), + PLL_36XX_RATE(394216000, 459, 7, 2, 49282), + PLL_36XX_RATE(333000000, 111, 2, 2, 0), + PLL_36XX_RATE(300000000, 100, 2, 2, 0), + PLL_36XX_RATE(266000000, 266, 3, 3, 0), + PLL_36XX_RATE(200000000, 200, 3, 3, 0), + PLL_36XX_RATE(166000000, 166, 3, 3, 0), + PLL_36XX_RATE(133000000, 266, 3, 4, 0), + PLL_36XX_RATE(100000000, 200, 3, 4, 0), + PLL_36XX_RATE(66000000, 176, 2, 5, 0), +}; + +static struct of_device_id ext_clk_match[] __initdata = { + { .compatible = "samsung,exynos5260-oscclk", .data = (void *)0, }, + { }, +}; + +static struct of_device_id cmu_subtype_match_table[] = { + { + .compatible = "exynos5260-cmu-all", + .data = (void *)CMU_TYPE_ALL, + }, { + .compatible = "exynos5260-cmu-top", + .data = (void *)CMU_TYPE_TOP, + }, { + .compatible = "exynos5260-cmu-peri", + .data = (void *)CMU_TYPE_PERI, + }, { + .compatible = "exynos5260-cmu-egl", + .data = (void *)CMU_TYPE_EGL, + }, { + .compatible = "exynos5260-cmu-kfc", + .data = (void *)CMU_TYPE_KFC, + }, { + .compatible = "exynos5260-cmu-g2d", + .data = (void *)CMU_TYPE_G2D, + }, { + .compatible = "exynos5260-cmu-mif", + .data = (void *)CMU_TYPE_MIF, + }, { + .compatible = "exynos5260-cmu-mfc", + .data = (void *)CMU_TYPE_MFC, + }, { + .compatible = "exynos5260-cmu-g3d", + .data = (void *)CMU_TYPE_G3D, + }, { + .compatible = "exynos5260-cmu-fsys", + .data = (void *)CMU_TYPE_FSYS, + }, { + .compatible = "exynos5260-cmu-aud", + .data = (void *)CMU_TYPE_AUD, + }, { + .compatible = "exynos5260-cmu-isp", + .data = (void *)CMU_TYPE_ISP, + }, { + .compatible = "exynos5260-cmu-gscl", + .data = (void *)CMU_TYPE_GSCL, + }, { + .compatible = "exynos5260-cmu-disp", + .data = (void *)CMU_TYPE_DISP, + }, { + /* end node */ + } +}; + +static struct samsung_pll_clock exynos5260_top_pll_clks[] __initdata = { + PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", + DISP_PLL_LOCK, DISP_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", + AUD_PLL_LOCK, AUD_PLL_CON0, + exynos5260_pll2650_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_egl_pll_clks[] __initdata = { + PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", + EGL_PLL_LOCK, EGL_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_kfc_pll_clks[] __initdata = { + PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", + KFC_PLL_LOCK, KFC_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_mif_pll_clks[] __initdata = { + PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", + MEM_PLL_LOCK, MEM_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll", + BUS_PLL_LOCK, BUS_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll", + MEDIA_PLL_LOCK, MEDIA_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_g3d_pll_clks[] __initdata = { + PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", + G3D_PLL_LOCK, G3D_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +void __init exynos5260_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + const struct of_device_id *match; + struct samsung_clk_reg_dump *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine soc\n", __func__); + + match = of_match_node(cmu_subtype_match_table, np); + + if (!match) + panic("%s: cmu type (%s) is not supported.\n", __func__, + np->name); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + if ((int)match->data == CMU_TYPE_AUD) { + rdump = exynos5260_aud_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_aud_clk_regs); + + ctx = samsung_clk_init(np, reg_base, AUD_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_aud_mux_clks, + ARRAY_SIZE(exynos5260_aud_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_aud_div_clks, + ARRAY_SIZE(exynos5260_aud_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_aud_gate_clks, + ARRAY_SIZE(exynos5260_aud_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_DISP) { + rdump = exynos5260_disp_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_disp_clk_regs); + + ctx = samsung_clk_init(np, reg_base, DISP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_disp_mux_clks, + ARRAY_SIZE(exynos5260_disp_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_disp_div_clks, + ARRAY_SIZE(exynos5260_disp_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_disp_gate_clks, + ARRAY_SIZE(exynos5260_disp_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_EGL) { + rdump = exynos5260_egl_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_egl_clk_regs); + + ctx = samsung_clk_init(np, reg_base, EGL_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_egl_pll_clks, + ARRAY_SIZE(exynos5260_egl_pll_clks), + reg_base); + + samsung_clk_register_mux(ctx, exynos5260_egl_mux_clks, + ARRAY_SIZE(exynos5260_egl_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_egl_div_clks, + ARRAY_SIZE(exynos5260_egl_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_egl_gate_clks, + ARRAY_SIZE(exynos5260_egl_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_FSYS) { + rdump = exynos5260_fsys_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_fsys_clk_regs); + + ctx = samsung_clk_init(np, reg_base, FSYS_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_fsys_mux_clks, + ARRAY_SIZE(exynos5260_fsys_mux_clks)); + samsung_clk_register_gate(ctx, exynos5260_fsys_gate_clks, + ARRAY_SIZE(exynos5260_fsys_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_G2D) { + rdump = exynos5260_g2d_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_g2d_clk_regs); + + ctx = samsung_clk_init(np, reg_base, G2D_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_g2d_mux_clks, + ARRAY_SIZE(exynos5260_g2d_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_g2d_div_clks, + ARRAY_SIZE(exynos5260_g2d_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_g2d_gate_clks, + ARRAY_SIZE(exynos5260_g2d_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_G3D) { + rdump = exynos5260_g3d_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_g3d_clk_regs); + + ctx = samsung_clk_init(np, reg_base, G3D_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + samsung_clk_register_pll(ctx, exynos5260_g3d_pll_clks, + ARRAY_SIZE(exynos5260_g3d_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_g3d_mux_clks, + ARRAY_SIZE(exynos5260_g3d_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_g3d_div_clks, + ARRAY_SIZE(exynos5260_g3d_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_g3d_gate_clks, + ARRAY_SIZE(exynos5260_g3d_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_GSCL) { + rdump = exynos5260_gscl_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_gscl_clk_regs); + + ctx = samsung_clk_init(np, reg_base, GSCL_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_gscl_mux_clks, + ARRAY_SIZE(exynos5260_gscl_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_gscl_div_clks, + ARRAY_SIZE(exynos5260_gscl_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_gscl_gate_clks, + ARRAY_SIZE(exynos5260_gscl_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_ISP) { + rdump = exynos5260_isp_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_isp_clk_regs); + + ctx = samsung_clk_init(np, reg_base, ISP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_isp_mux_clks, + ARRAY_SIZE(exynos5260_isp_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_isp_div_clks, + ARRAY_SIZE(exynos5260_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_isp_gate_clks, + ARRAY_SIZE(exynos5260_isp_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_KFC) { + rdump = exynos5260_kfc_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_kfc_clk_regs); + + ctx = samsung_clk_init(np, reg_base, KFC_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_kfc_pll_clks, + ARRAY_SIZE(exynos5260_kfc_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_kfc_mux_clks, + ARRAY_SIZE(exynos5260_kfc_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_kfc_div_clks, + ARRAY_SIZE(exynos5260_kfc_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_kfc_gate_clks, + ARRAY_SIZE(exynos5260_kfc_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_MFC) { + rdump = exynos5260_mfc_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_mfc_clk_regs); + + ctx = samsung_clk_init(np, reg_base, MFC_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_mfc_mux_clks, + ARRAY_SIZE(exynos5260_mfc_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_mfc_div_clks, + ARRAY_SIZE(exynos5260_mfc_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_mfc_gate_clks, + ARRAY_SIZE(exynos5260_mfc_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_MIF) { + rdump = exynos5260_mif_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_mif_clk_regs); + + ctx = samsung_clk_init(np, reg_base, MIF_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_mif_pll_clks, + ARRAY_SIZE(exynos5260_mif_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_mif_mux_clks, + ARRAY_SIZE(exynos5260_mif_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_mif_div_clks, + ARRAY_SIZE(exynos5260_mif_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_mif_gate_clks, + ARRAY_SIZE(exynos5260_mif_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_PERI) { + rdump = exynos5260_peri_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_peri_clk_regs); + + ctx = samsung_clk_init(np, reg_base, PERI_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_peri_mux_clks, + ARRAY_SIZE(exynos5260_peri_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_peri_div_clks, + ARRAY_SIZE(exynos5260_peri_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_peri_gate_clks, + ARRAY_SIZE(exynos5260_peri_gate_clks)); + + } else if ((int)match->data == CMU_TYPE_TOP) { + rdump = exynos5260_top_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_top_clk_regs); + + ctx = samsung_clk_init(np, reg_base, TOP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, + exynos5260_fixed_rate_ext_clks, + ARRAY_SIZE( + exynos5260_fixed_rate_ext_clks), + ext_clk_match); + + samsung_clk_register_fixed_rate(ctx, + exynos5260_fixed_rate_clks, + ARRAY_SIZE(exynos5260_fixed_rate_clks)); + + samsung_clk_register_pll(ctx, exynos5260_top_pll_clks, + ARRAY_SIZE(exynos5260_top_pll_clks), + + reg_base); + + samsung_clk_register_mux(ctx, exynos5260_top_mux_clks, + ARRAY_SIZE(exynos5260_top_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_top_div_clks, + ARRAY_SIZE(exynos5260_top_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_top_gate_clks, + ARRAY_SIZE(exynos5260_top_gate_clks)); + } else { + panic("%s: invalid cmu sub-type.\n", __func__); + }; + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +CLK_OF_DECLARE(exynos5260_clk, "samsung,exynos5260-clock", exynos5260_clk_init); + + + + + + + diff --git a/drivers/clk/samsung/clk-exynos5260.h b/drivers/clk/samsung/clk-exynos5260.h new file mode 100644 index 0000000..def73e6 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5260.h @@ -0,0 +1,496 @@ +#ifndef __CLK_EXYNOS5260_H +#define __CLK_EXYNOS5260_H + +#define CMU_TYPE_AUD 1 +#define CMU_TYPE_DISP 2 +#define CMU_TYPE_EGL 3 +#define CMU_TYPE_FSYS 4 +#define CMU_TYPE_G2D 5 +#define CMU_TYPE_G3D 6 +#define CMU_TYPE_GSCL 7 +#define CMU_TYPE_ISP 8 +#define CMU_TYPE_KFC 9 +#define CMU_TYPE_MFC 10 +#define CMU_TYPE_MIF 11 +#define CMU_TYPE_PERI 12 +#define CMU_TYPE_TOP 13 + +#define CMU_TYPE_ALL 14 + +/* +*Base address for different CMUs +*TODO: All Bases should be removed at earliest. +*/ +#define CMU_AUD_BASE 0x128C0000 +#define CMU_DISP_BASE 0x14550000 +#define CMU_EGL_BASE 0x10600000 +#define CMU_FSYS_BASE 0x122E0000 +#define CMU_G2D_BASE 0x10A00000 +#define CMU_G3D_BASE 0x11830000 +#define CMU_GSCL_BASE 0x13F00000 +#define CMU_ISP_BASE 0x133C0000 +#define CMU_KFC_BASE 0x10700000 +#define CMU_MFC_BASE 0x11090000 +#define CMU_MIF_BASE 0x10CE0000 +#define CMU_PERI_BASE 0x10200000 +#define CMU_TOP_BASE 0x10010000 + +#define AUD_REG(x) (x) +#define DISP_REG(x) (x) +#define EGL_REG(x) (x) +#define FSYS_REG(x) (x) +#define G2D_REG(x) (x) +#define G3D_REG(x) (x) +#define GSCL_REG(x) (x) +#define ISP_REG(x) (x) +#define KFC_REG(x) (x) +#define MFC_REG(x) (x) +#define MIF_REG(x) (x) +#define PERI_REG(x) (x) +#define TOP_REG(x) (x) + +/* +*Registers for CMU_AUD +*/ +#define MUX_SEL_AUD AUD_REG(0x0200) +#define MUX_ENABLE_AUD AUD_REG(0x0300) +#define MUX_STAT_AUD AUD_REG(0x0400) +#define MUX_IGNORE_AUD AUD_REG(0x0500) +#define DIV_AUD0 AUD_REG(0x0600) +#define DIV_AUD1 AUD_REG(0x0604) +#define DIV_STAT_AUD0 AUD_REG(0x0700) +#define DIV_STAT_AUD1 AUD_REG(0x0704) +#define EN_ACLK_AUD AUD_REG(0x0800) +#define EN_PCLK_AUD AUD_REG(0x0900) +#define EN_SCLK_AUD AUD_REG(0x0a00) +#define EN_IP_AUD AUD_REG(0x0b00) + +/* +*Registers for CMU_DISP +*/ +#define MUX_SEL_DISP0 DISP_REG(0x0200) +#define MUX_SEL_DISP1 DISP_REG(0x0204) +#define MUX_SEL_DISP2 DISP_REG(0x0208) +#define MUX_SEL_DISP3 DISP_REG(0x020C) +#define MUX_SEL_DISP4 DISP_REG(0x0210) +#define MUX_ENABLE_DISP0 DISP_REG(0x0300) +#define MUX_ENABLE_DISP1 DISP_REG(0x0304) +#define MUX_ENABLE_DISP2 DISP_REG(0x0308) +#define MUX_ENABLE_DISP3 DISP_REG(0x030c) +#define MUX_ENABLE_DISP4 DISP_REG(0x0310) +#define MUX_STAT_DISP0 DISP_REG(0x0400) +#define MUX_STAT_DISP1 DISP_REG(0x0404) +#define MUX_STAT_DISP2 DISP_REG(0x0408) +#define MUX_STAT_DISP3 DISP_REG(0x040c) +#define MUX_STAT_DISP4 DISP_REG(0x0410) +#define MUX_IGNORE_DISP0 DISP_REG(0x0500) +#define MUX_IGNORE_DISP1 DISP_REG(0x0504) +#define MUX_IGNORE_DISP2 DISP_REG(0x0508) +#define MUX_IGNORE_DISP3 DISP_REG(0x050c) +#define MUX_IGNORE_DISP4 DISP_REG(0x0510) +#define DIV_DISP DISP_REG(0x0600) +#define DIV_STAT_DISP DISP_REG(0x0700) +#define EN_ACLK_DISP DISP_REG(0x0800) +#define EN_PCLK_DISP DISP_REG(0x0900) +#define EN_SCLK_DISP0 DISP_REG(0x0a00) +#define EN_SCLK_DISP1 DISP_REG(0x0a04) +#define EN_IP_DISP DISP_REG(0x0b00) +#define EN_IP_DISP_BUS DISP_REG(0x0b04) + + +/* +*Registers for CMU_EGL +*/ +#define EGL_PLL_LOCK EGL_REG(0x0000) +#define EGL_DPLL_LOCK EGL_REG(0x0004) +#define EGL_PLL_CON0 EGL_REG(0x0100) +#define EGL_PLL_CON1 EGL_REG(0x0104) +#define EGL_PLL_FREQ_DET EGL_REG(0x010c) +#define EGL_DPLL_CON0 EGL_REG(0x0110) +#define EGL_DPLL_CON1 EGL_REG(0x0114) +#define EGL_DPLL_FREQ_DET EGL_REG(0x011c) +#define MUX_SEL_EGL EGL_REG(0x0200) +#define MUX_ENABLE_EGL EGL_REG(0x0300) +#define MUX_STAT_EGL EGL_REG(0x0400) +#define DIV_EGL EGL_REG(0x0600) +#define DIV_EGL_PLL_FDET EGL_REG(0x0604) +#define DIV_STAT_EGL EGL_REG(0x0700) +#define DIV_STAT_EGL_PLL_FDET EGL_REG(0x0704) +#define EN_ACLK_EGL EGL_REG(0x0800) +#define EN_PCLK_EGL EGL_REG(0x0900) +#define EN_SCLK_EGL EGL_REG(0x0a00) +#define EN_IP_EGL EGL_REG(0x0b00) +#define CLKOUT_CMU_EGL EGL_REG(0x0c00) +#define CLKOUT_CMU_EGL_DIV_STAT EGL_REG(0x0c04) +#define ARMCLK_STOPCTRL EGL_REG(0x1000) +#define EAGLE_EMA_CTRL EGL_REG(0x1008) +#define EAGLE_EMA_STATUS EGL_REG(0x100c) +#define PWR_CTRL EGL_REG(0x1020) +#define PWR_CTRL2 EGL_REG(0x1024) +#define CLKSTOP_CTRL EGL_REG(0x1028) +#define INTR_SPREAD_EN EGL_REG(0x1080) +#define INTR_SPREAD_USE_STANDBYWFI EGL_REG(0x1084) +#define INTR_SPREAD_BLOCKING_DURATION EGL_REG(0x1088) +#define CMU_EGL_SPARE0 EGL_REG(0x2000) +#define CMU_EGL_SPARE1 EGL_REG(0x2004) +#define CMU_EGL_SPARE2 EGL_REG(0x2008) +#define CMU_EGL_SPARE3 EGL_REG(0x200c) +#define CMU_EGL_SPARE4 EGL_REG(0x2010) + +/* +*Registers for CMU_FSYS +*/ + +#define MUX_SEL_FSYS0 FSYS_REG(0x0200) +#define MUX_SEL_FSYS1 FSYS_REG(0x0204) +#define MUX_ENABLE_FSYS0 FSYS_REG(0x0300) +#define MUX_ENABLE_FSYS1 FSYS_REG(0x0304) +#define MUX_STAT_FSYS0 FSYS_REG(0x0400) +#define MUX_STAT_FSYS1 FSYS_REG(0x0404) +#define MUX_IGNORE_FSYS0 FSYS_REG(0x0500) +#define MUX_IGNORE_FSYS1 FSYS_REG(0x0504) +#define EN_ACLK_FSYS FSYS_REG(0x0800) +#define EN_ACLK_FSYS_SECURE_RTIC FSYS_REG(0x0804) +#define EN_ACLK_FSYS_SECURE_SMMU_RTIC FSYS_REG(0x0808) +#define EN_PCLK_FSYS FSYS_REG(0x0900) +#define EN_SCLK_FSYS FSYS_REG(0x0a00) +#define EN_IP_FSYS FSYS_REG(0x0b00) +#define EN_IP_FSYS_SECURE_RTIC FSYS_REG(0x0b04) +#define EN_IP_FSYS_SECURE_SMMU_RTIC FSYS_REG(0x0b08) + +/* +*Registers for CMU_G2D +*/ + +#define MUX_SEL_G2D G2D_REG(0x0200) +#define MUX_ENABLE_G2D G2D_REG(0x0300) +#define MUX_STAT_G2D G2D_REG(0x0400) +#define DIV_G2D G2D_REG(0x0600) +#define DIV_STAT_G2D G2D_REG(0x0700) +#define EN_ACLK_G2D G2D_REG(0x0800) +#define EN_ACLK_G2D_SECURE_SSS G2D_REG(0x0804) +#define EN_ACLK_G2D_SECURE_SLIM_SSS G2D_REG(0x0808) +#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x080c) +#define EN_ACLK_G2D_SECURE_SMMU_SSS G2D_REG(0x0810) +#define EN_ACLK_G2D_SECURE_SMMU_MDMA G2D_REG(0x0814) +#define EN_ACLK_G2D_SECURE_SMMU_G2D G2D_REG(0x0818) +#define EN_PCLK_G2D G2D_REG(0x0900) +#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x0904) +#define EN_PCLK_G2D_SECURE_SMMU_SSS G2D_REG(0x0908) +#define EN_PCLK_G2D_SECURE_SMMU_MDMA G2D_REG(0x090c) +#define EN_PCLK_G2D_SECURE_SMMU_G2D G2D_REG(0x0910) +#define EN_IP_G2D G2D_REG(0x0b00) +#define EN_IP_G2D_SECURE_SSS G2D_REG(0x0b04) +#define EN_IP_G2D_SECURE_SLIM_SSS G2D_REG(0x0b08) +#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x0b0c) +#define EN_IP_G2D_SECURE_SMMU_SSS G2D_REG(0x0b10) +#define EN_IP_G2D_SECURE_SMMU_MDMA G2D_REG(0x0b14) +#define EN_IP_G2D_SECURE_SMMU_G2D G2D_REG(0x0b18) + +/* +*Registers for CMU_G3D +*/ + +#define G3D_PLL_LOCK G3D_REG(0x0000) +#define G3D_PLL_CON0 G3D_REG(0x0100) +#define G3D_PLL_CON1 G3D_REG(0x0104) +#define G3D_PLL_FDET G3D_REG(0x010c) +#define MUX_SEL_G3D G3D_REG(0x0200) +#define MUX_EN_G3D G3D_REG(0x0300) +#define MUX_STAT_G3D G3D_REG(0x0400) +#define MUX_IGNORE_G3D G3D_REG(0x0500) +#define DIV_G3D G3D_REG(0x0600) +#define DIV_G3D_PLL_FDET G3D_REG(0x0604) +#define DIV_STAT_G3D G3D_REG(0x0700) +#define DIV_STAT_G3D_PLL_FDET G3D_REG(0x0704) +#define EN_ACLK_G3D G3D_REG(0x0800) +#define EN_PCLK_G3D G3D_REG(0x0900) +#define EN_SCLK_G3D G3D_REG(0x0a00) +#define EN_IP_G3D G3D_REG(0x0b00) +#define CLKOUT_CMU_G3D G3D_REG(0x0c00) +#define CLKOUT_CMU_G3D_DIV_STAT G3D_REG(0x0c04) +#define G3DCLK_STOPCTRL G3D_REG(0x1000) +#define G3D_EMA_CTRL G3D_REG(0x1008) +#define G3D_EMA_STATUS G3D_REG(0x100c) + +/* +*Registers for CMU_GSCL +*/ + +#define MUX_SEL_GSCL GSCL_REG(0x0200) +#define MUX_EN_GSCL GSCL_REG(0x0300) +#define MUX_STAT_GSCL GSCL_REG(0x0400) +#define MUX_IGNORE_GSCL GSCL_REG(0x0500) +#define DIV_GSCL GSCL_REG(0x0600) +#define DIV_STAT_GSCL GSCL_REG(0x0700) +#define EN_ACLK_GSCL GSCL_REG(0x0800) +#define EN_ACLK_GSCL_FIMC GSCL_REG(0x0804) +#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0808) +#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x080c) +#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0810) +#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0814) +#define EN_PCLK_GSCL GSCL_REG(0x0900) +#define EN_PCLK_GSCL_FIMC GSCL_REG(0x0904) +#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0908) +#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x090c) +#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0910) +#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0914) +#define EN_SCLK_GSCL GSCL_REG(0x0a00) +#define EN_SCLK_GSCL_FIMC GSCL_REG(0x0a04) +#define EN_IP_GSCL GSCL_REG(0x0b00) +#define EN_IP_GSCL_FIMC GSCL_REG(0x0b04) +#define EN_IP_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0b08) +#define EN_IP_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x0b0c) +#define EN_IP_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0b10) +#define EN_IP_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0b14) + +/* +*Registers for CMU_ISP +*/ +#define MUX_SEL_ISP0 ISP_REG(0x0200) +#define MUX_SEL_ISP1 ISP_REG(0x0204) +#define MUX_ENABLE_ISP0 ISP_REG(0x0300) +#define MUX_ENABLE_ISP1 ISP_REG(0x0304) +#define MUX_STAT_ISP0 ISP_REG(0x0400) +#define MUX_STAT_ISP1 ISP_REG(0x0404) +#define MUX_IGNORE_ISP0 ISP_REG(0x0500) +#define MUX_IGNORE_ISP1 ISP_REG(0x0504) +#define DIV_ISP ISP_REG(0x0600) +#define DIV_STAT_ISP ISP_REG(0x0700) +#define EN_ACLK_ISP0 ISP_REG(0x0800) +#define EN_ACLK_ISP1 ISP_REG(0x0804) +#define EN_PCLK_ISP0 ISP_REG(0x0900) +#define EN_PCLK_ISP1 ISP_REG(0x0904) +#define EN_SCLK_ISP ISP_REG(0x0a00) +#define EN_IP_ISP0 ISP_REG(0x0b00) +#define EN_IP_ISP1 ISP_REG(0x0b04) + +/* +*Registers for CMU_KFC +*/ +#define KFC_PLL_LOCK KFC_REG(0x0000) +#define KFC_PLL_CON0 KFC_REG(0x0100) +#define KFC_PLL_CON1 KFC_REG(0x0104) +#define KFC_PLL_FDET KFC_REG(0x010c) +#define MUX_SEL_KFC0 KFC_REG(0x0200) +#define MUX_SEL_KFC2 KFC_REG(0x0208) +#define MUX_ENABLE_KFC0 KFC_REG(0x0300) +#define MUX_ENABLE_KFC2 KFC_REG(0x0308) +#define MUX_STAT_KFC0 KFC_REG(0x0400) +#define MUX_STAT_KFC2 KFC_REG(0x0408) +#define DIV_KFC KFC_REG(0x0600) +#define DIV_KFC_PLL_FDET KFC_REG(0x0604) +#define DIV_STAT_KFC KFC_REG(0x0700) +#define DIV_STAT_KFC_PLL_FDET KFC_REG(0x0704) +#define EN_ACLK_KFC KFC_REG(0x0800) +#define EN_PCLK_KFC KFC_REG(0x0900) +#define EN_SCLK_KFC KFC_REG(0x0a00) +#define EN_IP_KFC KFC_REG(0x0b00) +#define CLKOUT_CMU_KFC KFC_REG(0x0c00) +#define CLKOUT_CMU_KFC_DIV_STAT KFC_REG(0x0c04) +#define ARMCLK_STOPCTRL_KFC KFC_REG(0x1000) +#define ARM_EMA_CTRL KFC_REG(0x1008) +#define ARM_EMA_STATUS KFC_REG(0x100c) +#define PWR_CTRL_KFC KFC_REG(0x1020) +#define PWR_CTRL2_KFC KFC_REG(0x1024) +#define CLKSTOP_CTRL_KFC KFC_REG(0x1028) +#define INTR_SPREAD_ENABLE_KFC KFC_REG(0x1080) +#define INTR_SPREAD_USE_STANDBYWFI_KFC KFC_REG(0x1084) +#define INTR_SPREAD_BLOCKING_DURATION_KFC KFC_REG(0x1088) +#define CMU_KFC_SPARE0 KFC_REG(0x2000) +#define CMU_KFC_SPARE1 KFC_REG(0x2004) +#define CMU_KFC_SPARE2 KFC_REG(0x2008) +#define CMU_KFC_SPARE3 KFC_REG(0x200c) +#define CMU_KFC_SPARE4 KFC_REG(0x2010) + +/* +*Registers for CMU_MFC +*/ +#define MUX_SEL_MFC MFC_REG(0x0200) +#define MUX_ENABLE_MFC MFC_REG(0x0300) +#define MUX_STAT_MFC MFC_REG(0x0400) +#define DIV_MFC MFC_REG(0x0600) +#define DIV_STAT_MFC MFC_REG(0x0700) +#define EN_ACLK_MFC MFC_REG(0x0800) +#define EN_ACLK_SECURE_SMMU2_MFC MFC_REG(0x0804) +#define EN_PCLK_MFC MFC_REG(0x0900) +#define EN_PCLK_SECURE_SMMU2_MFC MFC_REG(0x0904) +#define EN_IP_MFC MFC_REG(0x0b00) +#define EN_IP_SECURE_SMMU2_MFC MFC_REG(0x0b04) + +/* +*Registers for CMU_MIF +*/ +#define MEM_PLL_LOCK MIF_REG(0x0000) +#define BUS_PLL_LOCK MIF_REG(0x0004) +#define MEDIA_PLL_LOCK MIF_REG(0x0008) +#define MEM_PLL_CON0 MIF_REG(0x0100) +#define MEM_PLL_CON1 MIF_REG(0x0104) +#define MEM_PLL_FDET MIF_REG(0x010c) +#define BUS_PLL_CON0 MIF_REG(0x0110) +#define BUS_PLL_CON1 MIF_REG(0x0114) +#define BUS_PLL_FDET MIF_REG(0x011c) +#define MEDIA_PLL_CON0 MIF_REG(0x0120) +#define MEDIA_PLL_CON1 MIF_REG(0x0124) +#define MEDIA_PLL_FDET MIF_REG(0x012c) +#define MUX_SEL_MIF MIF_REG(0x0200) +#define MUX_ENABLE_MIF MIF_REG(0x0300) +#define MUX_STAT_MIF MIF_REG(0x0400) +#define MUX_IGNORE_MIF MIF_REG(0x0500) +#define DIV_MIF MIF_REG(0x0600) +#define DIV_MIF_PLL_FDET MIF_REG(0x0604) +#define DIV_STAT_MIF MIF_REG(0x0700) +#define DIV_STAT_MIF_PLL_FDET MIF_REG(0x0704) +#define EN_ACLK_MIF MIF_REG(0x0800) +#define EN_ACLK_MIF_SECURE_DREX1_TZ MIF_REG(0x0804) +#define EN_ACLK_MIF_SECURE_DREX0_TZ MIF_REG(0x0808) +#define EN_ACLK_MIF_SECURE_INTMEM MIF_REG(0x080c) +#define EN_PCLK_MIF MIF_REG(0x0900) +#define EN_PCLK_MIF_SECURE_MONOCNT MIF_REG(0x0904) +#define EN_PCLK_MIF_SECURE_RTC_APBIF MIF_REG(0x0908) +#define EN_PCLK_MIF_SECURE_DREX1_TZ MIF_REG(0x090c) +#define EN_PCLK_MIF_SECURE_DREX0_TZ MIF_REG(0x0910) +#define EN_SCLK_MIF MIF_REG(0x0a00) +#define EN_IP_MIF MIF_REG(0x0b00) +#define EN_IP_MIF_SECURE_MONOCNT MIF_REG(0x0b04) +#define EN_IP_MIF_SECURE_RTC_APBIF MIF_REG(0x0b08) +#define EN_IP_MIF_SECURE_DREX1_TZ MIF_REG(0x0b0c)EN_ACLK_MIF_SECURE_INTMEM +#define EN_IP_MIF_SECURE_DREX0_TZ MIF_REG(0x0b10) +#define EN_IP_MIF_SECURE_INTEMEM MIF_REG(0x0b14) +#define CLKOUT_CMU_MIF_DIV_STAT MIF_REG(0x0c04) +#define DREX_FREQ_CTRL MIF_REG(0x1000) +#define PAUSE MIF_REG(0x1004) +#define DDRPHY_LOCK_CTRL MIF_REG(0x1008) +#define CLKOUT_CMU_MIF MIF_REG(0xcb00) + +/* +*Registers for CMU_PERI +*/ +#define MUX_SEL_PERI PERI_REG(0x0200) +#define MUX_SEL_PERI1 PERI_REG(0x0204) +#define MUX_ENABLE_PERI PERI_REG(0x0300) +#define MUX_ENABLE_PERI1 PERI_REG(0x0304) +#define MUX_STAT_PERI PERI_REG(0x0400) +#define MUX_STAT_PERI1 PERI_REG(0x0404) +#define MUX_IGNORE_PERI PERI_REG(0x0500) +#define MUX_IGNORE_PERI1 PERI_REG(0x0504) +#define DIV_PERI PERI_REG(0x0600) +#define DIV_STAT_PERI PERI_REG(0x0700) +#define EN_PCLK_PERI0 PERI_REG(0x0800) +#define EN_PCLK_PERI1 PERI_REG(0x0804) +#define EN_PCLK_PERI2 PERI_REG(0x0808) +#define EN_PCLK_PERI3 PERI_REG(0x080c) +#define EN_PCLK_PERI_SECURE_CHIPID PERI_REG(0x0810) +#define EN_PCLK_PERI_SECURE_PROVKEY0 PERI_REG(0x0814) +#define EN_PCLK_PERI_SECURE_PROVKEY1 PERI_REG(0x0818) +#define EN_PCLK_PERI_SECURE_SECKEY PERI_REG(0x081c) +#define EN_PCLK_PERI_SECURE_ANTIRBKCNT PERI_REG(0x0820) +#define EN_PCLK_PERI_SECURE_TOP_RTC PERI_REG(0x0824) +#define EN_PCLK_PERI_SECURE_TZPC PERI_REG(0x0828) +#define EN_SCLK_PERI PERI_REG(0x0a00) +#define EN_SCLK_PERI_SECURE_TOP_RTC PERI_REG(0x0a04) +#define EN_IP_PERI0 PERI_REG(0x0b00) +#define EN_IP_PERI1 PERI_REG(0x0b04) +#define EN_IP_PERI2 PERI_REG(0x0b08) +#define EN_IP_PERI_SECURE_CHIPID PERI_REG(0x0b0c) +#define EN_IP_PERI_SECURE_PROVKEY0 PERI_REG(0x0b10) +#define EN_IP_PERI_SECURE_PROVKEY1 PERI_REG(0x0b14) +#define EN_IP_PERI_SECURE_SECKEY PERI_REG(0x0b18) +#define EN_IP_PERI_SECURE_ANTIRBKCNT PERI_REG(0x0b1c) +#define EN_IP_PERI_SECURE_TOP_RTC PERI_REG(0x0b20) +#define EN_IP_PERI_SECURE_TZPC PERI_REG(0x0b24) + +/* +*Registers for CMU_TOP +*/ +#define DISP_PLL_LOCK TOP_REG(0x0000) +#define AUD_PLL_LOCK TOP_REG(0x0004) +#define DISP_PLL_CON0 TOP_REG(0x0100) +#define DISP_PLL_CON1 TOP_REG(0x0104) +#define DISP_PLL_FDET TOP_REG(0x0108) +#define AUD_PLL_CON0 TOP_REG(0x0110) +#define AUD_PLL_CON1 TOP_REG(0x0114) +#define AUD_PLL_CON2 TOP_REG(0x0118) +#define AUD_PLL_FDET TOP_REG(0x011c) +#define MUX_SEL_TOP_PLL0 TOP_REG(0x0200) +#define MUX_SEL_TOP_MFC TOP_REG(0x0204) +#define MUX_SEL_TOP_G2D TOP_REG(0x0208) +#define MUX_SEL_TOP_GSCL TOP_REG(0x020c) +#define MUX_SEL_TOP_ISP10 TOP_REG(0x0214) +#define MUX_SEL_TOP_ISP11 TOP_REG(0x0218) +#define MUX_SEL_TOP_DISP0 TOP_REG(0x021c) +#define MUX_SEL_TOP_DISP1 TOP_REG(0x0220) +#define MUX_SEL_TOP_BUS TOP_REG(0x0224) +#define MUX_SEL_TOP_PERI0 TOP_REG(0x0228) +#define MUX_SEL_TOP_PERI1 TOP_REG(0x022c) +#define MUX_SEL_TOP_FSYS TOP_REG(0x0230) +#define MUX_ENABLE_TOP_PLL0 TOP_REG(0x0300) +#define MUX_ENABLE_TOP_MFC TOP_REG(0x0304) +#define MUX_ENABLE_TOP_G2D TOP_REG(0x0308) +#define MUX_ENABLE_TOP_GSCL TOP_REG(0x030c) +#define MUX_ENABLE_TOP_ISP10 TOP_REG(0x0314) +#define MUX_ENABLE_TOP_ISP11 TOP_REG(0x0318) +#define MUX_ENABLE_TOP_DISP0 TOP_REG(0x031c) +#define MUX_ENABLE_TOP_DISP1 TOP_REG(0x0320) +#define MUX_ENABLE_TOP_BUS TOP_REG(0x0324) +#define MUX_ENABLE_TOP_PERI0 TOP_REG(0x0328) +#define MUX_ENABLE_TOP_PERI1 TOP_REG(0x032c) +#define MUX_ENABLE_TOP_FSYS TOP_REG(0x0330) +#define MUX_STAT_TOP_PLL0 TOP_REG(0x0400) +#define MUX_STAT_TOP_MFC TOP_REG(0x0404) +#define MUX_STAT_TOP_G2D TOP_REG(0x0408) +#define MUX_STAT_TOP_GSCL TOP_REG(0x040c) +#define MUX_STAT_TOP_ISP10 TOP_REG(0x0414) +#define MUX_STAT_TOP_ISP11 TOP_REG(0x0418) +#define MUX_STAT_TOP_DISP0 TOP_REG(0x041c) +#define MUX_STAT_TOP_DISP1 TOP_REG(0x0420) +#define MUX_STAT_TOP_BUS TOP_REG(0x0424) +#define MUX_STAT_TOP_PERI0 TOP_REG(0x0428) +#define MUX_STAT_TOP_PERI1 TOP_REG(0x042c) +#define MUX_STAT_TOP_FSYS TOP_REG(0x0430) +#define MUX_IGNORE_TOP_PLL0 TOP_REG(0x0500) +#define MUX_IGNORE_TOP_MFC TOP_REG(0x0504) +#define MUX_IGNORE_TOP_G2D TOP_REG(0x0508) +#define MUX_IGNORE_TOP_GSCL TOP_REG(0x050c) +#define MUX_IGNORE_TOP_ISP10 TOP_REG(0x0514) +#define MUX_IGNORE_TOP_ISP11 TOP_REG(0x0518) +#define MUX_IGNORE_TOP_DISP0 TOP_REG(0x051c) +#define MUX_IGNORE_TOP_DISP1 TOP_REG(0x0520) +#define MUX_IGNORE_TOP_BUS TOP_REG(0x0524) +#define MUX_IGNORE_TOP_PERI0 TOP_REG(0x0528) +#define MUX_IGNORE_TOP_PERI1 TOP_REG(0x052c) +#define MUX_IGNORE_TOP_FSYS TOP_REG(0x0530) +#define DIV_TOP_G2D_MFC TOP_REG(0x0600) +#define DIV_TOP_GSCL_ISP0 TOP_REG(0x0604) +#define DIV_TOP_ISP10 TOP_REG(0x0608) +#define DIV_TOP_ISP11 TOP_REG(0x060c) +#define DIV_TOP_DISP TOP_REG(0x0610) +#define DIV_TOP_BUS TOP_REG(0x0614) +#define DIV_TOP_PERI0 TOP_REG(0x0618) +#define DIV_TOP_PERI1 TOP_REG(0x061c) +#define DIV_TOP_PERI2 TOP_REG(0x0620) +#define DIV_TOP_FSYS0 TOP_REG(0x0624) +#define DIV_TOP_FSYS1 TOP_REG(0x0628) +#define DIV_TOP_HPM TOP_REG(0x062c) +#define DIV_TOP_PLL_FDET TOP_REG(0x0630) +#define DIV_STAT_TOP_G2D_MFC TOP_REG(0x0700) +#define DIV_STAT_TOP_GSCL_ISP0 TOP_REG(0x0704) +#define DIV_STAT_TOP_ISP10 TOP_REG(0x0708) +#define DIV_STAT_TOP_ISP11 TOP_REG(0x070c) +#define DIV_STAT_TOP_DISP TOP_REG(0x0710) +#define DIV_STAT_TOP_BUS TOP_REG(0x0714) +#define DIV_STAT_TOP_PERI0 TOP_REG(0x0718) +#define DIV_STAT_TOP_PERI1 TOP_REG(0x071c) +#define DIV_STAT_TOP_PERI2 TOP_REG(0x0720) +#define DIV_STAT_TOP_FSYS0 TOP_REG(0x0724) +#define DIV_STAT_TOP_FSYS1 TOP_REG(0x0728) +#define DIV_STAT_TOP_HPM TOP_REG(0x072c) +#define DIV_STAT_TOP_PLL_FDET TOP_REG(0x0730) +#define EN_ACLK_TOP TOP_REG(0x0800) +#define EN_SCLK_TOP TOP_REG(0x0a00) +#define EN_IP_TOP TOP_REG(0x0b00) +#define CLKOUT_CMU_TOP TOP_REG(0x0c00) +#define CLKOUT_CMU_TOP_DIV_STAT TOP_REG(0x0c04) + +#endif /*__CLK_EXYNOS5260_H */ + diff --git a/include/dt-bindings/clk/exynos5260-clk.h b/include/dt-bindings/clk/exynos5260-clk.h new file mode 100644 index 0000000..73763e4 --- /dev/null +++ b/include/dt-bindings/clk/exynos5260-clk.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Provides Constants for Exynos5260 clocks. +*/ + +#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H +#define _DT_BINDINGS_CLK_EXYNOS5260_H + +#define ID_NONE 0 + +/* + * Clock names: XXXXXX_YYYYY_ZZZZZ + * |------| |----| |----| + * cmu type IP +*/ + +/* list of cocks for CMU_TOP */ +#define FIN_PLL 1 +#define TOP_FOUT_DISP_PLL 2 +#define TOP_FOUT_AUD_PLL 3 +#define TOP_SCLK_MMC0 4 +#define TOP_SCLK_MMC1 5 +#define TOP_SCLK_MMC2 6 +#define TOP_SCLK_HDMIPHY 7 +#define TOP_SCLK_FIMD1 8 +#define TOP_MOUT_FIMD1 9 +#define TOP_MOUT_DISP_PLL 10 +#define TOP_NR_CLK 11 + +/* list of cocks for CMU_EGL */ +#define EGL_FOUT_EGL_PLL 1 +#define EGL_FOUT_EGL_DPLL 2 +#define EGL_NR_CLK 3 + +/* list of cocks for CMU_KFC */ +#define KFC_FOUT_KFC_PLL 1 +#define KFC_NR_CLK 2 + +/* list of cocks for CMU_MIF */ +#define MIF_FOUT_MEM_PLL 1 +#define MIF_FOUT_BUS_PLL 2 +#define MIF_FOUT_MEDIA_PLL 3 +#define MIF_NR_CLK 4 + +/* list of cocks for CMU_G3D */ +#define G3D_FOUT_G3D_PLL 1 +#define G3D_ACLK_G3D 2 +#define G3D_NR_CLK 3 + +/* list of cocks for CMU_AUD */ +#define AUD_SCLK_AUD_UART 1 +#define AUD_SCLK_PCM 2 +#define AUD_ACLK_SRAMC 3 +#define AUD_ACLK_DMAC 4 +#define AUD_PCLK_AUD_UART 5 +#define AUD_PCLK_PCM 6 +#define AUD_PCLK_I2S 7 +#define AUD_PCLK_DMAC 8 +#define AUD_NR_CLK 9 + +/* list of cocks for CMU_MFC */ +#define MFC_ACLK_MFC 1 +#define MFC_PCLK_MFC 2 +#define MFC_PCLK_SMMU_MFC0 3 +#define MFC_PCLK_SMMU_MFC1 4 +#define MFC_NR_CLK 5 + +/* list of cocks for CMU_GSCL */ +#define GSCL_ACLK_GSCL0 1 +#define GSCL_ACLK_GSCL1 2 +#define GSCL_PCLK_GSCL0 3 +#define GSCL_PCLK_GSCL1 4 +#define GSCL_PCLK_SMMU_GSCL0 5 +#define GSCL_PCLK_SMMU_GSCL1 6 +#define GSCL_NR_CLK 7 + +/* list of cocks for CMU_FSYS */ +#define FSYS_HCLK_TSI 1 +#define FSYS_PCLK_GPIO 2 +#define FSYS_HCLK_USBHOST20 3 +#define FSYS_ACLK_USBDRD30 4 +#define FSYS_ACLK_PDMA0 5 +#define FSYS_ACLK_RTIC 6 +#define FSYS_PCLK_SMMU_RTIC 7 +#define FSYS_PHYCLK_USBDRD30 8 +#define FSYS_PHYCLK_USBHOST20 9 +#define FSYS_HCLK_MMC0 10 +#define FSYS_HCLK_MMC1 11 +#define FSYS_HCLK_MMC2 12 +#define FSYS_HCLK_SROMC 13 +#define FSYS_NR_CLK 14 + +/* list of cocks for CMU_PERI */ +#define PERI_PCLK_ADC 1 +#define PERI_PCLK_TMU1 2 +#define PERI_PCLK_TMU0 3 +#define PERI_PCLK_SPI0 4 +#define PERI_PCLK_SPI1 5 +#define PERI_PCLK_SPI2 6 +#define PERI_PCLK_I2S1 7 +#define PERI_PCLK_PWM 8 +#define PERI_PCLK_SPDIF 9 +#define PERI_PCLK_ABB 10 +#define PERI_PCLK_MCT 11 +#define PERI_PCLK_HSIC0 12 +#define PERI_PCLK_HSIC1 13 +#define PERI_PCLK_HSIC2 14 +#define PERI_PCLK_HSIC3 15 +#define PERI_PCLK_UART0 16 +#define PERI_PCLK_UART1 17 +#define PERI_PCLK_UART2 18 +#define PERI_PCLK_PCM1 19 +#define PERI_PCLK_WDT_EGL 20 +#define PERI_PCLK_WDT_KFC 21 +#define PERI_PCLK_CHIPID 22 +#define PERI_CLK_TMU0 23 +#define PERI_CLK_TMU1 24 +#define PERI_CLK_TMU2 25 +#define PERI_CLK_TMU3 26 +#define PERI_CLK_TMU4 27 +#define PERI_PCLK_I2C4 28 +#define PERI_PCLK_I2C5 29 +#define PERI_PCLK_I2C6 30 +#define PERI_PCLK_I2C7 31 +#define PERI_PCLK_I2C8 32 +#define PERI_PCLK_I2C9 33 +#define PERI_PCLK_I2C10 34 +#define PERI_PCLK_I2C11 35 +#define PERI_PCLK_TOP_RTC 36 +#define PERI_SCLK_RTC 37 +#define PERI_SCLK_UART0 38 +#define PERI_SCLK_UART1 39 +#define PERI_SCLK_UART2 40 +#define PERI_SCLK_SPDIF 41 +#define PERI_SCLK_SPI0 42 +#define PERI_SCLK_SPI1 43 +#define PERI_SCLK_SPI2 44 +#define PERI_SCLK_I2S 45 +#define PERI_SCLK_PCM1 46 +#define PERI_NR_CLK 47 + +/* list of cocks for CMU_DISP */ +#define DISP_SCLK_HDMI 1 +#define DISP_SCLK_PIXEL 2 +#define DISP_ACLK_MIXER 3 +#define DISP_ACLK_HDMI 4 +#define DISP_ACLK_FIMD1 5 +#define DISP_PCLK_SMMU_TV 6 +#define DISP_PCLK_SMMU_FIMD1M1 7 +#define DISP_PCLK_SMMU_FIMD1M0 8 +#define DISP_PCLK_DSIM1 9 +#define DISP_PCLK_HDMIPHY 10 +#define DISP_PCLK_HDMI 11 +#define DISP_DP 12 +#define DISP_MOUT_HDMI_PHY_PIXEL 13 +#define DISP_NR_CLK 14 + +/* list of cocks for CMU_G2D */ +#define G2D_ACLK_MDMA 1 +#define G2D_NR_CLK 2 + +#define ISP_NR_CLK 0 + +#endif

[7/7] clk/exynos5260: add clock file for exynos5260

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