From patchwork Wed Nov 13 11:58:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 290904 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C0AD92C00BC for ; Wed, 13 Nov 2013 23:23:42 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759024Ab3KMMXl (ORCPT ); Wed, 13 Nov 2013 07:23:41 -0500 Received: from fallback8.mail.ru ([94.100.176.136]:53371 "EHLO fallback8.mail.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758511Ab3KMMXl (ORCPT ); Wed, 13 Nov 2013 07:23:41 -0500 Received: from smtp45.i.mail.ru (smtp45.i.mail.ru [94.100.177.105]) by fallback8.mail.ru (mPOP.Fallback_MX) with ESMTP id 4FF5744F5EAD for ; Wed, 13 Nov 2013 15:58:57 +0400 (MSK) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=Message-Id:Date:Subject:Cc:To:From; bh=LVNcGEKJmvU+mIFov0KdUjtwALvmNnHzb2wfYBrzkZU=; b=iNTAfGxrSyIxUeQa84lj5Z7PdGVX2Xfd+rUZhbGatxyV0aFVo4AhLzeA7P5mYP4RwRzYURm4E0rbq50tuQsjiVl7yKhI3fK2hMRz44BmvDPJPm1EpCprhfGA7MVkqL1+23HYBgd3DZ1LL2kqdR4TUbCpaEE9GJmUvjuWqIG8Pyw=; Received: from [217.119.30.118] (port=18616 helo=shc.milas.spb.ru) by smtp45.i.mail.ru with esmtpa (envelope-from ) id 1VgZ5V-0005g4-Ub; Wed, 13 Nov 2013 15:58:26 +0400 From: Alexander Shiyan To: linux-mtd@lists.infradead.org Cc: devicetree@vger.kernel.org, David Woodhouse , Artem Bityutskiy , Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Russell King , Eric Miao , Haojian Zhuang , Alexander Shiyan Subject: [PATCH v5 1/3] mtd: nand: gpio: Add DT property to automatically determine bus width Date: Wed, 13 Nov 2013 15:58:02 +0400 Message-Id: <1384343884-29622-1-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.8.1.5 X-Spam: Not detected X-Mras: Ok Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds a property to automatically determine the NAND bus width by CFI/ONFI information from chip. This property works if the bus width is not specified explicitly. Signed-off-by: Alexander Shiyan --- .../devicetree/bindings/mtd/gpio-control-nand.txt | 3 +++ drivers/mtd/nand/gpio.c | 16 ++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt index 36ef07d..fe4e960 100644 --- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt @@ -19,6 +19,9 @@ Optional properties: defaults to 1 byte. - chip-delay : chip dependent delay for transferring data from array to read registers (tR). If not present then a default of 20us is used. +- gpio-control-nand,bank-width-auto : Device bus width is determined + automatically by CFI/ONFI information from chip if "bank-width" + parameter is omitted (Boolean). - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read location used to guard against bus reordering with regards to accesses to the GPIO's and the NAND flash data bus. If present, then after changing diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c index e826f89..8ec731d 100644 --- a/drivers/mtd/nand/gpio.c +++ b/drivers/mtd/nand/gpio.c @@ -116,6 +116,9 @@ static int gpio_nand_get_config_of(const struct device *dev, dev_err(dev, "invalid bank-width %u\n", val); return -EINVAL; } + } else if (of_property_read_bool(dev->of_node, + "gpio-control-nand,bank-width-auto")) { + plat->options |= NAND_BUSWIDTH_AUTO; } plat->gpio_rdy = of_get_gpio(dev->of_node, 0); @@ -223,6 +226,15 @@ static int gpio_nand_probe(struct platform_device *pdev) if (IS_ERR(chip->IO_ADDR_R)) return PTR_ERR(chip->IO_ADDR_R); + ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat); + if (ret) + return ret; + + /* Only 8-bit bus wide is possible if size is 1 */ + if (resource_size(res) < 2) + gpiomtd->plat.options &= ~(NAND_BUSWIDTH_16 | + NAND_BUSWIDTH_AUTO); + res = gpio_nand_get_io_sync(pdev); if (res) { gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res); @@ -230,10 +242,6 @@ static int gpio_nand_probe(struct platform_device *pdev) return PTR_ERR(gpiomtd->io_sync); } - ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat); - if (ret) - return ret; - ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE"); if (ret) return ret;