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[v4,00/10] Add Milk-V Pioneer RISC-V board support

Message ID cover.1696433229.git.unicorn_wang@outlook.com
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Series Add Milk-V Pioneer RISC-V board support | expand

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Chen Wang Oct. 4, 2023, 3:37 p.m. UTC 
From: Chen Wang <unicorn_wang@outlook.com>

Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.

Now only support basic uart drivers to boot up into a basic console.

Thanks,
Chen

---

Changes in v4:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [6].
  - Update bindings files for sg2042 clint as per intput from reviewers:
    - rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer
      to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
    - rename compatible strings accordingly.
  - Update dts as per input from reviewers: don't use macro for cpus's isa
    properties; use new compatible strings for mtimer/mswi of clint.
  - Use only one email-address for SoB.

Changes in v3 [v3]:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [5].
  - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
  - updated maintainers info. for sophgo devicetree
  - remove the quirk changes for uart
  - updated dts, such as:
    - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
    - update l2 cache node's name
    - remove memory and pmu nodes
  - fixed other issues as per input from reviewers.

Changes in v2 [v2]:
  The patch series is based on v6.6-rc1. You can simply review or test
  the patches at the link [4].
  - Improve format for comment of commitments as per input from last review.
  - Improve format of DTS as per input from last review.
  - Remove numa related stuff from DTS. This part is just for optimization, may
    add it later if really needed.

Changes in v1:
   The patch series is based on v6.6-rc1. Due to it is not sent in thread,
   I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
   quick reference. You can simply review or test the patches at the link [3].

[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
[v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
[v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
[v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
[v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
[v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
[v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
[v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
[v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
[v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
[v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
[v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
[v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
[v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
[v2]:https://lore.kernel.org/linux-riscv/cover.1695189879.git.wangchen20@iscas.ac.cn/
[v3]:https://lore.kernel.org/linux-riscv/cover.1695804418.git.unicornxw@gmail.com/

---

Chen Wang (8):
  riscv: Add SOPHGO SOC family Kconfig support
  dt-bindings: vendor-prefixes: add milkv/sophgo
  dt-bindings: riscv: add sophgo sg2042 bindings
  dt-bindings: riscv: Add T-HEAD C920 compatibles
  dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
  riscv: dts: add initial Sophgo SG2042 SoC device tree
  riscv: dts: sophgo: add Milk-V Pioneer board device tree
  riscv: defconfig: enable SOPHGO SoC

Inochi Amaoto (2):
  dt-bindings: timer: Add Sophgo sg2042 CLINT timer
  dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi

 .../sifive,plic-1.0.0.yaml                    |    1 +
 .../thead,c900-aclint-mswi.yaml               |   43 +
 .../devicetree/bindings/riscv/cpus.yaml       |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
 .../timer/thead,c900-aclint-mtimer.yaml       |   43 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
 MAINTAINERS                                   |    7 +
 arch/riscv/Kconfig.socs                       |    5 +
 arch/riscv/boot/dts/Makefile                  |    1 +
 arch/riscv/boot/dts/sophgo/Makefile           |    3 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 2000 +++++++++++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  325 +++
 arch/riscv/configs/defconfig                  |    1 +
 14 files changed, 2481 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi


base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d

Comments

Chen Wang Oct. 6, 2023, 1:05 a.m. UTC | #1 
On 2023/10/4 23:37, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Now only support basic uart drivers to boot up into a basic console.
>
> Thanks,
> Chen
>
> ---
>
> Changes in v4:
>    The patch series is based on v6.6-rc1. You can simply review or test
>    the patches at the link [6].
>    - Update bindings files for sg2042 clint as per intput from reviewers:
>      - rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer
>        to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
>      - rename compatible strings accordingly.
>    - Update dts as per input from reviewers: don't use macro for cpus's isa
>      properties; use new compatible strings for mtimer/mswi of clint.
>    - Use only one email-address for SoB.
>
> Changes in v3 [v3]:
>    The patch series is based on v6.6-rc1. You can simply review or test
>    the patches at the link [5].
>    - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
>    - updated maintainers info. for sophgo devicetree
>    - remove the quirk changes for uart
>    - updated dts, such as:
>      - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
>      - update l2 cache node's name
>      - remove memory and pmu nodes
>    - fixed other issues as per input from reviewers.
>
> Changes in v2 [v2]:
>    The patch series is based on v6.6-rc1. You can simply review or test
>    the patches at the link [4].
>    - Improve format for comment of commitments as per input from last review.
>    - Improve format of DTS as per input from last review.
>    - Remove numa related stuff from DTS. This part is just for optimization, may
>      add it later if really needed.
>
> Changes in v1:
>     The patch series is based on v6.6-rc1. Due to it is not sent in thread,
>     I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
>     quick reference. You can simply review or test the patches at the link [3].
>
> [1]: https://milkv.io/pioneer
> [2]: https://en.sophgo.com/product/introduce/sg2042.html
> [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> [5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
> [6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
> [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> [v2]:https://lore.kernel.org/linux-riscv/cover.1695189879.git.wangchen20@iscas.ac.cn/
> [v3]:https://lore.kernel.org/linux-riscv/cover.1695804418.git.unicornxw@gmail.com/
>
> ---
>
> Chen Wang (8):
>    riscv: Add SOPHGO SOC family Kconfig support
>    dt-bindings: vendor-prefixes: add milkv/sophgo
>    dt-bindings: riscv: add sophgo sg2042 bindings
>    dt-bindings: riscv: Add T-HEAD C920 compatibles
>    dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
>    riscv: dts: add initial Sophgo SG2042 SoC device tree
>    riscv: dts: sophgo: add Milk-V Pioneer board device tree
>    riscv: defconfig: enable SOPHGO SoC
>
> Inochi Amaoto (2):
>    dt-bindings: timer: Add Sophgo sg2042 CLINT timer
>    dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
>
>   .../sifive,plic-1.0.0.yaml                    |    1 +
>   .../thead,c900-aclint-mswi.yaml               |   43 +
>   .../devicetree/bindings/riscv/cpus.yaml       |    1 +
>   .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
>   .../timer/thead,c900-aclint-mtimer.yaml       |   43 +
>   .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
>   MAINTAINERS                                   |    7 +
>   arch/riscv/Kconfig.socs                       |    5 +
>   arch/riscv/boot/dts/Makefile                  |    1 +
>   arch/riscv/boot/dts/sophgo/Makefile           |    3 +
>   arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 2000 +++++++++++++++++
>   .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
>   arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  325 +++
>   arch/riscv/configs/defconfig                  |    1 +
>   14 files changed, 2481 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
>   create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
>   create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
>   create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
>   create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>   create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>   create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
>
> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d


This is the correct patchset, please review this one. Because my 
incorrect operation resulted in two patchsets with the same name being 
sent earlier, but they were incomplete. Sorry for the confusion.

Thanks,

Chen
Conor Dooley Oct. 6, 2023, 2:31 p.m. UTC | #2 
From: Conor Dooley <conor.dooley@microchip.com>

On Wed, 04 Oct 2023 23:37:20 +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
> 
> Now only support basic uart drivers to boot up into a basic console.
> 
> [...]

[10/10] riscv: defconfig: enable SOPHGO SoC
        https://git.kernel.org/conor/c/a4bbe6e3d9f6

b4 is confused, but I applied the whole series, temporarily, to a
"sophgo" branch. IIRC I asked for the defconfig patch to have
savedefconfig run it it, so I did that and amended the patch.
More notably, I changed the commit message for the aclint patch, to
drop the discussion about incorrect use of the sifive,clint compatible.
That meant that 90% of the commit message vanished, so I'd like you guys
to take a look and see if the new text works for you.
If it is acceptable, I'll merge in both this series and the milkv duo
stuff. Acks on that series from one of the folks added as a maintainer
here are still appreciated and will be applied.

Thanks,
Conor.
Jisheng Zhang Oct. 6, 2023, 2:36 p.m. UTC | #3 
On Wed, Oct 04, 2023 at 11:44:06PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Milk-V Pioneer motherboard is powered by SG2042.
> 
> SG2042 is server grade chip with high performance, low power
> consumption and high data throughput.
> Key features:
> - 64 RISC-V cpu cores
> - 4 cores per cluster, 16 clusters on chip
> - More info is available at [1].
> 
> Currently only support booting into console with only uart,
> other features will be added soon later.
> 
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Co-developed-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> 
> Link: https://en.sophgo.com/product/introduce/sg2042.html [1]
> ---
>  MAINTAINERS                                 |    1 +
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  325 +++
>  3 files changed, 2326 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 97cb8abcfeee..fedf042e5fb4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
>  M:	Chao Wei <chao.wei@sophgo.com>
>  M:	Chen Wang <unicorn_wang@outlook.com>
>  S:	Maintained
> +F:	arch/riscv/boot/dts/sophgo/
>  F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
>  
>  SOUND
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> new file mode 100644
> index 000000000000..b136b6c4128c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -0,0 +1,2000 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
...

> +		intc: interrupt-controller@7090000000 {
> +			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
> +			interrupt-controller;
> +			interrupts-extended =
> +				<&cpu0_intc 0xffffffff>,  <&cpu0_intc 9>,

-1 may not be correct, is machine external interrupt(id: 11) supported?

Thanks
Chen Wang Oct. 7, 2023, 5:29 a.m. UTC | #4 
On 2023/10/6 22:36, Jisheng Zhang wrote:
> On Wed, Oct 04, 2023 at 11:44:06PM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Milk-V Pioneer motherboard is powered by SG2042.
>>
>> SG2042 is server grade chip with high performance, low power
>> consumption and high data throughput.
>> Key features:
>> - 64 RISC-V cpu cores
>> - 4 cores per cluster, 16 clusters on chip
>> - More info is available at [1].
>>
>> Currently only support booting into console with only uart,
>> other features will be added soon later.
>>
>> Reviewed-by: Guo Ren <guoren@kernel.org>
>> Acked-by: Chao Wei <chao.wei@sophgo.com>
>> Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>> Co-developed-by: Inochi Amaoto <inochiama@outlook.com>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>>
>> Link: https://en.sophgo.com/product/introduce/sg2042.html [1]
>> ---
>>   MAINTAINERS                                 |    1 +
>>   arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++++
>>   arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  325 +++
>>   3 files changed, 2326 insertions(+)
>>   create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>   create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 97cb8abcfeee..fedf042e5fb4 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
>>   M:	Chao Wei <chao.wei@sophgo.com>
>>   M:	Chen Wang <unicorn_wang@outlook.com>
>>   S:	Maintained
>> +F:	arch/riscv/boot/dts/sophgo/
>>   F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
>>   
>>   SOUND
>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>> new file mode 100644
>> index 000000000000..b136b6c4128c
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>> @@ -0,0 +1,2000 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
>> + */
> ...
>
>> +		intc: interrupt-controller@7090000000 {
>> +			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
>> +			#address-cells = <0>;
>> +			#interrupt-cells = <2>;
>> +			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
>> +			interrupt-controller;
>> +			interrupts-extended =
>> +				<&cpu0_intc 0xffffffff>,  <&cpu0_intc 9>,
> -1 may not be correct, is machine external interrupt(id: 11) supported?

Just double-checked with sophgo IC engineers, sg2042 plic supports 
external interrupt, so 11 should be better, I will try to fix this in v5.

Thanks for your kindly reminder, Jisheng.


>
> Thanks
Chen Wang Oct. 7, 2023, 8:07 a.m. UTC | #5 
On 2023/10/6 22:31, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> On Wed, 04 Oct 2023 23:37:20 +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
>> in a standard mATX form factor. Add minimal device
>> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>>
>> Now only support basic uart drivers to boot up into a basic console.
>>
>> [...]
> [10/10] riscv: defconfig: enable SOPHGO SoC
>          https://git.kernel.org/conor/c/a4bbe6e3d9f6
>
> b4 is confused, but I applied the whole series, temporarily, to a
> "sophgo" branch. IIRC I asked for the defconfig patch to have
> savedefconfig run it it, so I did that and amended the patch.
Thanks, I'll pay attention on this next time.
> More notably, I changed the commit message for the aclint patch, to
> drop the discussion about incorrect use of the sifive,clint compatible.
> That meant that 90% of the commit message vanished, so I'd like you guys
> to take a look and see if the new text works for you.

Yes, it works for us, thanks.

> If it is acceptable, I'll merge in both this series and the milkv duo
> stuff. Acks on that series from one of the folks added as a maintainer
> here are still appreciated and will be applied.

Acked-by: Chen Wang <unicorn_wang@outlook.com>

Due to commnents from Jisheng, I want to continue changes DTS on plic 
node, I have submitted v5 patchset, can you please pick and merge with 
this? v5 also contains the changes you have made on "sophgo" branch.

Thanks,

Chen

>
> Thanks,
> Conor.