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[v6,0/4] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs

Message ID IA1PR20MB4953C774D41EDF1EADB6EC18BB6D2@IA1PR20MB4953.namprd20.prod.outlook.com
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Series riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs | expand

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Inochi Amaoto Jan. 14, 2024, 4:15 a.m. UTC 
Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.

Changed from v5:
1. rebased to mainline master tree
2. add SG2000 clock support.
3. fix document link

Changed from v4:
1. improve code for patch 2
2. remove the already applied bindings
https://lore.kernel.org/all/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com/

Changed from v3:
1. improve comment of patch 3
2. cleanup the include of patch 2

Changed from v2:
1. remove clock-names from bindings.
2. remove clock-frequency node of DT from previous patch.
3. change some unused clock to bypass mode to avoid unlockable PLL.

Changed from v1:
1. fix license issues.


Inochi Amaoto (4):
  dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC
  clk: sophgo: Add CV1800/SG2000 series clock controller driver
  riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
  riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC

 .../bindings/clock/sophgo,cv1800-clk.yaml     |    3 +-
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi       |    4 +
 arch/riscv/boot/dts/sophgo/cv1812h.dtsi       |    4 +
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi        |   22 +-
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/sophgo/Kconfig                    |   12 +
 drivers/clk/sophgo/Makefile                   |    7 +
 drivers/clk/sophgo/clk-cv1800.c               | 1545 +++++++++++++++++
 drivers/clk/sophgo/clk-cv1800.h               |  123 ++
 drivers/clk/sophgo/clk-cv18xx-common.c        |   66 +
 drivers/clk/sophgo/clk-cv18xx-common.h        |   81 +
 drivers/clk/sophgo/clk-cv18xx-ip.c            |  905 ++++++++++
 drivers/clk/sophgo/clk-cv18xx-ip.h            |  265 +++
 drivers/clk/sophgo/clk-cv18xx-pll.c           |  425 +++++
 drivers/clk/sophgo/clk-cv18xx-pll.h           |  119 ++
 16 files changed, 3577 insertions(+), 6 deletions(-)
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-cv1800.c
 create mode 100644 drivers/clk/sophgo/clk-cv1800.h
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h

--
2.43.0

Comments

Chen Wang Jan. 31, 2024, 3:44 a.m. UTC | #1 
On 2024/1/14 12:17, Inochi Amaoto wrote:
> Add clock generator node for CV1800B and CV1812H.
>
> Until now, It uses DT override to minimize duplication. This may
> change in the future. See the last link for the discussion on
> maintaining DT of CV1800 series.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
> Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>

> ---
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++
>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 ++++
>   arch/riscv/boot/dts/sophgo/cv18xx.dtsi  | 6 ++++++
>   3 files changed, 14 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index 165e9e320a8c..baf641829e72 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -16,3 +16,7 @@ &plic {
>   &clint {
>   	compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
>   };
> +
> +&clk {
> +	compatible = "sophgo,cv1800-clk";
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> index 3e7a942f5c1a..7fa4c1e2d1da 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -22,3 +22,7 @@ &plic {
>   &clint {
>   	compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
>   };
> +
> +&clk {
> +	compatible = "sophgo,cv1810-clk";
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 2d6f4a4b1e58..6ea1b2784db9 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -53,6 +53,12 @@ soc {
>   		dma-noncoherent;
>   		ranges;
>
> +		clk: clock-controller@3002000 {
> +			reg = <0x03002000 0x1000>;
> +			clocks = <&osc>;
> +			#clock-cells = <1>;
> +		};
> +
>   		gpio0: gpio@3020000 {
>   			compatible = "snps,dw-apb-gpio";
>   			reg = <0x3020000 0x1000>;
> --
> 2.43.0
>
Chen Wang Jan. 31, 2024, 3:46 a.m. UTC | #2 
On 2024/1/14 12:17, Inochi Amaoto wrote:
> Add missing clocks of uart node for CV1800B and CV1812H.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 16 +++++++++++-----
>   1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 6ea1b2784db9..7c88cbe8e91d 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -5,6 +5,7 @@
>    */
>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/sophgo,cv1800.h>
>
>   / {
>   	#address-cells = <1>;
> @@ -135,7 +136,8 @@ uart0: serial@4140000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04140000 0x100>;
>   			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -145,7 +147,8 @@ uart1: serial@4150000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04150000 0x100>;
>   			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -155,7 +158,8 @@ uart2: serial@4160000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04160000 0x100>;
>   			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -165,7 +169,8 @@ uart3: serial@4170000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04170000 0x100>;
>   			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> @@ -175,7 +180,8 @@ uart4: serial@41c0000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x041c0000 0x100>;
>   			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&osc>;
> +			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
>   			status = "disabled";
> --
> 2.43.0
>