mbox series

[0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

Message ID 20250519160448.209461-1-18255117159@163.com
Headers show
Series Relax max-link-speed check to support PCIe Gen5/Gen6 | expand

Message

Hans Zhang May 19, 2025, 4:04 p.m. UTC 
This patch series extends PCIe Gen5/Gen6 support for the max-link-speed
property across device tree bindings and kernel validation logic.

With PCIe 6.0 now supported in the Linux kernel and industry IP providers
like Synopsys/Cadence offering PCIe 6.0-compatible IPs, existing device
tree bindings and checks for max-link-speed (limited to Gen1~Gen4) no
longer align with hardware capabilities.

Documentation updates:

Patch 1/3 extends the PCI host controller binding (pci.txt) to explicitly
include Gen5/Gen6.

Patch 2/3 updates the PCI endpoint binding (pci-ep.yaml) with the same
extension.

Kernel validation fix:

Patch 3/3 relaxes the max-link-speed check in of_pci_get_max_link_speed()
to accept values up to 6, ensuring compatibility with newer generations.

These changes ensure that device tree configurations for modern PCIe
controllers (e.g., Synopsys/Cadence IP-based designs) can fully utilize
Gen5/Gen6 speeds without DT validation errors.

---
In my impression, they have already obtained the relevant certifications.

e.g.:
Synopsys:
https://www.synopsys.com/dw/ipdir.php?ds=dwc_pcie6_controller

Cadence:
https://www.cadence.com/en_US/home/tools/silicon-solutions/protocol-ip/pcie-and-compute-express-link/controller-for-pcie-and-cxl/controller-for-pcie.html
---

Hans Zhang (3):
  dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6
  dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
  PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

 Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +-
 Documentation/devicetree/bindings/pci/pci.txt     | 5 +++--
 drivers/pci/of.c                                  | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)


base-commit: fee3e843b309444f48157e2188efa6818bae85cf