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[v2,0/5] mips: bmips: improve handling of RAC and CBR addr

Message ID 20240503212139.5811-1-ansuelsmth@gmail.com
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Series mips: bmips: improve handling of RAC and CBR addr | expand

Message

Christian Marangi May 3, 2024, 9:20 p.m. UTC 
Hi,

this simple series improve handling of RAC and CBR address and try to
upstream these simple patch we have in OpenWrt for a while.

The first patch fix a straight kernel panic where some Bootloader might
enable RAC but misconfigure the CBR address. The current logic only
check if RAC is enabled but doesn't verify if the CBR address is usable.

The DMA sync function cause a kernel panic for invalid write. (as CBR is
0 or something like 0xa)

The second is preparation for making the CBR address configurable in DT.
Since this address doesn't change, we can cache it and reference it with
a local variable instead of calling the register to access the value.

The 4th patch make it configurable with 2 DT property, one to actually
set the reg and the other to force set it.

The first property is used when CBR is set to 0. The second property is
to force it if the Bootloader sets it to something wrong.

If the CBR value is not 0 and is not forced with the second property a
WARN is printed and the DT value is ignored.

The 5th patch enable RAC on BMIPS4350 and the 5th patch is a micro
optimization to skip more call on DMA sync to save as resource as
possible on low spec devices. (since DMA sync is called many times for
the Ethernet Switch and we can reference the bool instead of checking
the CPU type everytime)

These has been tested on BCM6358 (HG556a) and BCM6368 (VH4032N) and
reported correct functionality.

Changes v2:
- Prefix brcm vendor in the added property
- Drop last patch (cpu switch from DMA sync)
- Validate CBR addr from DT to be outside DRAM
- Reduce indentation in DT CBR check
- Reduce delta and use local variable for CBR where possible
- Fix and improve typo and spelling mistake
- Use 0xf instead of 0xa for BCM6358 RAC enable

Christian Marangi (4):
  mips: bmips: BCM6358: make sure CBR is correctly set
  mips: bmips: rework and cache CBR addr handling
  dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
  mips: bmips: setup: make CBR address configurable

Daniel González Cabanelas (1):
  mips: bmips: enable RAC on BMIPS4350

 .../devicetree/bindings/mips/brcm/soc.yaml    | 32 ++++++++++++++
 arch/mips/bmips/dma.c                         |  2 +-
 arch/mips/bmips/setup.c                       | 42 ++++++++++++++++++-
 arch/mips/include/asm/bmips.h                 |  1 +
 arch/mips/kernel/smp-bmips.c                  | 21 +++++++++-
 5 files changed, 93 insertions(+), 5 deletions(-)

Comments

Florian Fainelli May 3, 2024, 9:23 p.m. UTC | #1 
On 5/3/24 14:20, Christian Marangi wrote:
> It was discovered that some device have CBR address set to 0 causing
> kernel panic when arch_sync_dma_for_cpu_all is called.
> 
> This was notice in situation where the system is booted from TP1 and
> BMIPS_GET_CBR() returns 0 instead of a valid address and
> !!(read_c0_brcm_cmt_local() & (1 << 31)); not failing.
> 
> The current check whether RAC flush should be disabled or not are not
> enough hence lets check if CBR is a valid address or not.
> 
> Fixes: ab327f8acdf8 ("mips: bmips: BCM6358: disable RAC flush for TP1")
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Florian Fainelli May 3, 2024, 9:23 p.m. UTC | #2 
On 5/3/24 14:20, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
> 
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Florian Fainelli May 3, 2024, 9:33 p.m. UTC | #3 
On 5/3/24 14:21, Christian Marangi wrote:
> From: Daniel González Cabanelas <dgcbueu@gmail.com>
> 
> The data RAC is left disabled by the bootloader in some SoCs, at least in
> the core it boots from.
> Enabling this feature increases the performance up to +30% depending on the
> task.
> 
> Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> [ rework code and reduce code duplication ]
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>