| Message ID | 20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org |
|---|---|
| Headers | show |
| Series | drm/msm: Add support for the A750 GPU found on the SM8650 platform | expand |
On Fri, 16 Feb 2024 12:03:47 +0100, Neil Armstrong wrote: > Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU > doesn't have an HWCFG block but a separate register set. > > The missing registers are added in the a6xx.xml.h file that would > require a subsequent sync and the non-existent hwcfg is handled > in a6xx_set_hwcg(). > > [...] Applied SMMU binding changes to will (for-joerg/arm-smmu/bindings), thanks! [2/7] dt-bindings: arm-smmu: Fix SM8[45]50 GPU SMMU 'if' condition https://git.kernel.org/will/c/2777781ca9b6 [3/7] dt-bindings: arm-smmu: Document SM8650 GPU SMMU https://git.kernel.org/will/c/8a05f74d567a Cheers,
On 2/16/24 12:03, Neil Armstrong wrote: > Add GPU nodes for the SM8650 platform. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ > 1 file changed, 166 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 62e6ae93a9a8..27dcef27b6ad 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { > #reset-cells = <1>; > }; > > + gpu: gpu@3d00000 { > + compatible = "qcom,adreno-43051401", "qcom,adreno"; > + reg = <0x0 0x03d00000 0x0 0x40000>, > + <0x0 0x03d9e000 0x0 0x1000>, > + <0x0 0x03d61000 0x0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", > + "cx_mem", > + "cx_dbgc"; > + > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; > + > + iommus = <&adreno_smmu 0 0x0>, > + <&adreno_smmu 1 0x0>; > + > + operating-points-v2 = <&gpu_opp_table>; > + > + qcom,gmu = <&gmu>; > + > + status = "disabled"; > + > + zap-shader { > + memory-region = <&gpu_micro_code_mem>; > + }; > + > + /* Speedbin needs more work on A740+, keep only lower freqs */ > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-680000000 { > + opp-hz = /bits/ 64 <680000000>; > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + }; I got a memo from krzk that we should be sorting OPPs low-to-high, could you please reorder these (and under gmu)? Otherwise lgtm Konrad
On 12/03/2024 01:20, Konrad Dybcio wrote: > > > On 2/16/24 12:03, Neil Armstrong wrote: >> Add GPU nodes for the SM8650 platform. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 166 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index 62e6ae93a9a8..27dcef27b6ad 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { >> #reset-cells = <1>; >> }; >> + gpu: gpu@3d00000 { >> + compatible = "qcom,adreno-43051401", "qcom,adreno"; >> + reg = <0x0 0x03d00000 0x0 0x40000>, >> + <0x0 0x03d9e000 0x0 0x1000>, >> + <0x0 0x03d61000 0x0 0x800>; >> + reg-names = "kgsl_3d0_reg_memory", >> + "cx_mem", >> + "cx_dbgc"; >> + >> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; >> + >> + iommus = <&adreno_smmu 0 0x0>, >> + <&adreno_smmu 1 0x0>; >> + >> + operating-points-v2 = <&gpu_opp_table>; >> + >> + qcom,gmu = <&gmu>; >> + >> + status = "disabled"; >> + >> + zap-shader { >> + memory-region = <&gpu_micro_code_mem>; >> + }; >> + >> + /* Speedbin needs more work on A740+, keep only lower freqs */ >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-680000000 { >> + opp-hz = /bits/ 64 <680000000>; >> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >> + }; > > I got a memo from krzk that we should be sorting OPPs low-to-high, > could you please reorder these (and under gmu)? Ack, I also add 3 more OPPs that works with all speedbins. Neil > > Otherwise lgtm > > Konrad
Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The missing registers are added in the a6xx.xml.h file that would require a subsequent sync and the non-existent hwcfg is handled in a6xx_set_hwcg(). The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. This adds: - the GMU and SMMU bindings - DRM driver changes - DT nodes Dependencies: None Tested using Mesa's !26934 Merge Request [0] on the SM8650-QRD and with kmscube & vkcube to test basic rendering. [0] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934 Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v3: - Fixed smmu bindings if condition for GMU smmu - Collected reviews - Link to v2: https://lore.kernel.org/r/20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org Changes in v2: - Added separate a6xx.xml.h sync from https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576 - Collected review tags - Inlined skip_programming - Use A7XX_RBBM_CGC_P2S_STATUS_TXDONE instead of BIT(0) - Drop now useless placeholder comment - Removed interconnect properties - Rebased on current linux-next - Link to v1: https://lore.kernel.org/r/20240212-topic-sm8650-gpu-v1-0-708a40b747b5@linaro.org --- Neil Armstrong (7): dt-bindings: display/msm/gmu: Document Adreno 750 GMU dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition dt-bindings: arm-smmu: Document SM8650 GPU SMMU drm/msm/a6xx: Add missing regs for A750 drm/msm: add support for A750 GPU arm64: dts: qcom: sm8650: add GPU nodes arm64: dts: qcom: sm8650-qrd: enable GPU .../devicetree/bindings/display/msm/gmu.yaml | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml | 17 ++- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 + arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 ++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +- 9 files changed, 247 insertions(+), 8 deletions(-) --- base-commit: 2c3b09aac00d7835023bbc4473ee06696be64fa8 change-id: 20240208-topic-sm8650-gpu-489d5e2c2b17 Best regards,