| Message ID | 20230920065459.12738-1-quic_tengfan@quicinc.com |
|---|---|
| Headers | show |
| Series | soc: qcom: Add uart console support for SM4450 | expand |
On 9/20/23 08:54, Tengfei Fan wrote: > Add device node for RPMH and Global clock controller on Qualcomm > SM4450 platform. > > Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm4450.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi > index 3d9d3b5e9510..c27f17a41699 100644 > --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi > @@ -3,6 +3,8 @@ > * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > +#include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sm4450-gcc.h> These should be sorted alphabetically. [...] > + rpmhcc: clock-controller { > + compatible = "qcom,sm4450-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board>; property property-names Konrad
On 9/20/23 08:54, Tengfei Fan wrote: > Add base description of UART and TLMM nodes which helps SM4450 > boot to shell with console on boards with this SoC. > > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> > --- The SoC change must be separate from the board change. [...] Please leave a comment explaining what these GPIOs are used for. > +&tlmm { > + gpio-reserved-ranges = <0 4>, <136 1>; > +}; [...] > + qupv3_id_0: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x00ac0000 0x0 0x2000>; > + ranges; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; property property-names [...] > + > + uart7: serial@a88000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0 0x00a88000 0 0x4000>; Use 0x0 consistently. > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; property property-names > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; ditto [...] > + compatible = "qcom,sm4450-tlmm"; > + reg = <0 0x0f100000 0 0x300000>; Use 0x0 consistently > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 137>; > + wakeup-parent = <&pdc>; > + > + qup_uart7_rx: qup-uart7-rx-state { > + pins = "gpio23"; > + function = "qup1_se2_l2"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart7_tx: qup-uart7-tx-state { > + pins = "gpio22"; > + function = "qup1_se2_l2"; > + drive-strength = <2>; > + bias-disable; > + }; > + }; > + > intc: interrupt-controller@17200000 { > compatible = "arm,gic-v3"; > reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ > @@ -476,7 +525,6 @@ > clocks = <&xo_board>; > }; > }; > - Totally unrelated change, fix the patch introducing it instead. Konrad
On 9/20/23 08:54, Tengfei Fan wrote: > From: Ajit Pandey <quic_ajipan@quicinc.com> > > Add apps_rsc node and cmd_db memory region for sm4450. > > Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi > index c4e5b33f5169..3d9d3b5e9510 100644 > --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi > @@ -5,6 +5,7 @@ > > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > > / { > interrupt-parent = <&intc>; > @@ -328,6 +329,18 @@ > }; > }; > > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + aop_cmd_db_mem: cmd-db@80860000 { > + compatible = "qcom,cmd-db"; > + reg = <0x0 0x80860000 0x0 0x20000>; > + no-map; > + }; > + }; > + > soc: soc@0 { > #address-cells = <2>; > #size-cells = <2>; > @@ -419,6 +432,28 @@ > status = "disabled"; > }; > }; > + > + apps_rsc: rsc@17a00000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0 0x17a00000 0 0x10000>, > + <0 0x17a10000 0 0x10000>, > + <0 0x17a20000 0 0x10000>; 0x0 for consistency > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + label = "apps_rsc"; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > + <WAKE_TCS 3>, <CONTROL_TCS 0>; You haven't addressed Bjorn's comment about the number of CONTROL_TCSes, are you sure 0 is correct? Konrad
在 9/20/2023 6:14 PM, Konrad Dybcio 写道: > > > On 9/20/23 08:54, Tengfei Fan wrote: >> From: Ajit Pandey <quic_ajipan@quicinc.com> >> >> Add apps_rsc node and cmd_db memory region for sm4450. >> >> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++ >> 1 file changed, 35 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> index c4e5b33f5169..3d9d3b5e9510 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> @@ -5,6 +5,7 @@ >> #include <dt-bindings/gpio/gpio.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >> / { >> interrupt-parent = <&intc>; >> @@ -328,6 +329,18 @@ >> }; >> }; >> + reserved_memory: reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + aop_cmd_db_mem: cmd-db@80860000 { >> + compatible = "qcom,cmd-db"; >> + reg = <0x0 0x80860000 0x0 0x20000>; >> + no-map; >> + }; >> + }; >> + >> soc: soc@0 { >> #address-cells = <2>; >> #size-cells = <2>; >> @@ -419,6 +432,28 @@ >> status = "disabled"; >> }; >> }; >> + >> + apps_rsc: rsc@17a00000 { >> + compatible = "qcom,rpmh-rsc"; >> + reg = <0 0x17a00000 0 0x10000>, >> + <0 0x17a10000 0 0x10000>, >> + <0 0x17a20000 0 0x10000>; > 0x0 for consistency Hi Konrad, Yes, I will update "0" to "0x0" for consistency. > >> + reg-names = "drv-0", "drv-1", "drv-2"; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; >> + label = "apps_rsc"; >> + qcom,tcs-offset = <0xd00>; >> + qcom,drv-id = <2>; >> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >> + <WAKE_TCS 3>, <CONTROL_TCS 0>; > You haven't addressed Bjorn's comment about the number of > CONTROL_TCSes, are you sure 0 is correct? > > Konrad I got confirm from internal power team, setting CONTROL_TCS with 0 is correct.
在 9/20/2023 6:00 PM, Konrad Dybcio 写道: > > > On 9/20/23 08:54, Tengfei Fan wrote: >> Add device node for RPMH and Global clock controller on Qualcomm >> SM4450 platform. >> >> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm4450.dtsi | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> index 3d9d3b5e9510..c27f17a41699 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> @@ -3,6 +3,8 @@ >> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights >> reserved. >> */ >> +#include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/clock/qcom,sm4450-gcc.h> > These should be sorted alphabetically.Yes, I will sort these alphabetically. > > [...] > >> + rpmhcc: clock-controller { >> + compatible = "qcom,sm4450-rpmh-clk"; >> + #clock-cells = <1>; >> + clock-names = "xo"; >> + clocks = <&xo_board>; > property > property-names > > Konrad Hi Konrad, Sure, I will adjust these noeds.
在 9/20/2023 6:03 PM, Konrad Dybcio 写道: > > > On 9/20/23 08:54, Tengfei Fan wrote: >> Add base description of UART and TLMM nodes which helps SM4450 >> boot to shell with console on boards with this SoC. >> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- > The SoC change must be separate from the board change. > > [...] > > Please leave a comment explaining what these GPIOs are > used for. I checked these gpio setting, the gpio0 ~ gpio3 are for NFC eSE SPI, gpio136 is for LPI Debug. >> +&tlmm { >> + gpio-reserved-ranges = <0 4>, <136 1>; >> +}; > > [...] > >> + qupv3_id_0: geniqup@ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x00ac0000 0x0 0x2000>; >> + ranges; >> + clock-names = "m-ahb", "s-ahb"; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > property > property-names I will adjust these nodes. > > [...] > >> + >> + uart7: serial@a88000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0 0x00a88000 0 0x4000>; > Use 0x0 consistently. I will update this for using "0x0" instead of "0". > >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > property > property-names I will adjust these nodes. > >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; > ditto I will adjust these nodes. > > [...] > >> + compatible = "qcom,sm4450-tlmm"; >> + reg = <0 0x0f100000 0 0x300000>; > Use 0x0 consistently I will update this for using "0x0" instead of "0" > >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + gpio-ranges = <&tlmm 0 0 137>; >> + wakeup-parent = <&pdc>; >> + >> + qup_uart7_rx: qup-uart7-rx-state { >> + pins = "gpio23"; >> + function = "qup1_se2_l2"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + qup_uart7_tx: qup-uart7-tx-state { >> + pins = "gpio22"; >> + function = "qup1_se2_l2"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + }; >> + >> intc: interrupt-controller@17200000 { >> compatible = "arm,gic-v3"; >> reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >> @@ -476,7 +525,6 @@ >> clocks = <&xo_board>; >> }; >> }; >> - > Totally unrelated change, fix the patch introducing it instead. > > Konrad Hi Konrad, I will remove this rnrelated change.
在 9/20/2023 6:00 PM, Konrad Dybcio 写道: > > > On 9/20/23 08:54, Tengfei Fan wrote: >> Add device node for RPMH and Global clock controller on Qualcomm >> SM4450 platform. >> >> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm4450.dtsi | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> index 3d9d3b5e9510..c27f17a41699 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> @@ -3,6 +3,8 @@ >> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights >> reserved. >> */ >> +#include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/clock/qcom,sm4450-gcc.h> > These should be sorted alphabetically. > Hi Konrad, I think these included header files already were sorted alphabetically(r -> s), so there are unnecessary for adjust them again, right? > [...] > >> + rpmhcc: clock-controller { >> + compatible = "qcom,sm4450-rpmh-clk"; >> + #clock-cells = <1>; >> + clock-names = "xo"; >> + clocks = <&xo_board>; > property > property-names > > Konrad
This series add base description of UART, TLMM, RPMHCC, GCC and RPMh PD nodes which helps SM4450 boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- This patch series depends on below patch series: "[PATCH v2 0/4] clk: qcom: Add support for GCC and RPMHCC on SM4450" https://lore.kernel.org/linux-arm-msm/20230909123431.1725728-1-quic_ajipan@quicinc.com/ "[PATCH v3 0/2] pinctl: qcom: Add SM4450 pinctrl driver" https://lore.kernel.org/linux-arm-msm/20230920064739.12562-1-quic_tengfan@quicinc.com/ v2 -> v3: - fix dtbs_check warning - remove interconnect, iommu, scm and tcsr related code - rearrangement dt node - remove smmu, scm and tcsr related documentation update - enable CONFIG_SM_GCC_4450 in defconfig related patch v1 -> v2: - setting "qcom,rpmh-rsc" compatible to the first property - keep order by unit address - move tlmm node into soc node - update arm,smmu.yaml - add enable pinctrl and interconnect defconfig patches - remove blank line - redo dtbs_check check previous discussion here: [1] v2: https://lore.kernel.org/linux-arm-msm/20230915021509.25773-1-quic_tengfan@quicinc.com [2] v2: https://lore.kernel.org/linux-arm-msm/20230908065847.28382-1-quic_tengfan@quicinc.com Ajit Pandey (1): arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node Tengfei Fan (4): dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc arm64: dts: qcom: sm4450: Add RPMH and Global clock arm64: dts: qcom: add uart console support for SM4450 arm64: defconfig: enable clock controller and pinctrl for SM4450 .../interrupt-controller/qcom,pdc.yaml | 1 + arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++- arch/arm64/boot/dts/qcom/sm4450.dtsi | 106 ++++++++++++++++++ arch/arm64/configs/defconfig | 2 + 4 files changed, 125 insertions(+), 2 deletions(-) base-commit: dfa449a58323de195773cf928d99db4130702bf7