| Message ID | 20230918125853.2249187-1-contact@jookia.org |
|---|---|
| Headers | show |
| Series | Add FS035VG158 panel | expand |
On 9/18/2023 5:58 AM, John Watts wrote: > The current code waits after resets for 5 to 20 milliseconds. > This is appropriate when resetting a sleeping panel, but an awake panel > requires at least 120ms of waiting. > > Sleep for 150ms so the panel always completes it reset properly. > > Signed-off-by: John Watts <contact@jookia.org> Hi John, Just wondering, is there some context to this change? I.e., was this made to fix a specific issue? This seems like a pretty significant increase in wait time so, if it's not a fix, I'm not sure if this would be an improvement on the current behavior. Thanks, Jessica Zhang > --- > drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > index 90dea21f9856..2526b123b1f5 100644 > --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > @@ -258,7 +258,7 @@ static int nv3052c_prepare(struct drm_panel *panel) > gpiod_set_value_cansleep(priv->reset_gpio, 1); > usleep_range(10, 1000); > gpiod_set_value_cansleep(priv->reset_gpio, 0); > - usleep_range(5000, 20000); > + msleep(150); > > for (i = 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) { > err = mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd, > -- > 2.42.0 >
On 9/18/2023 5:58 AM, John Watts wrote: > The panel needs us to wait 120ms between exiting and entering sleep. > Guarantee that by always waiting 150ms before entering sleep mode. Hi John, Same question as the last patch -- is this a fix for something? Thanks, Jessica Zhang > > Signed-off-by: John Watts <contact@jookia.org> > --- > drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > index 2526b123b1f5..307335d0f1fc 100644 > --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > @@ -289,6 +289,9 @@ static int nv3052c_unprepare(struct drm_panel *panel) > struct mipi_dbi *dbi = &priv->dbi; > int err; > > + /* Wait 150ms in case we just exited sleep mode */ > + msleep(150); > + > err = mipi_dbi_command(dbi, MIPI_DCS_ENTER_SLEEP_MODE); > if (err) > dev_err(priv->dev, "Unable to enter sleep mode: %d\n", err); > -- > 2.42.0 >
On 9/18/2023 5:58 AM, John Watts wrote: > This display is extremely similar to the LTK035C5444T, but still has > some minor variations in panel initialization. > > Signed-off-by: John Watts <contact@jookia.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> > --- > .../gpu/drm/panel/panel-newvision-nv3052c.c | 223 ++++++++++++++++++ > 1 file changed, 223 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > index 2b24c684a8ac..a42c38d93f52 100644 > --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c > @@ -238,6 +238,201 @@ static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { > { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 > }; > > +static const struct nv3052c_reg fs035vg158_panel_regs[] = { > + // EXTC Command set enable, select page 1 > + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, > + // Mostly unknown registers > + { 0xe3, 0x00 }, > + { 0x40, 0x00 }, > + { 0x03, 0x40 }, > + { 0x04, 0x00 }, > + { 0x05, 0x03 }, > + { 0x08, 0x00 }, > + { 0x09, 0x07 }, > + { 0x0a, 0x01 }, > + { 0x0b, 0x32 }, > + { 0x0c, 0x32 }, > + { 0x0d, 0x0b }, > + { 0x0e, 0x00 }, > + { 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N > + { 0x24, 0x0c }, > + { 0x25, 0x06 }, > + { 0x26, 0x14 }, > + { 0x27, 0x14 }, > + { 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t > + { 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t > + { 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t > + { 0x28, 0x40 }, > + { 0x29, 0x01 }, > + { 0x2a, 0xdf }, > + { 0x49, 0x3c }, > + { 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t > + { 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t > + { 0xa0, 0x55 }, > + { 0xa1, 0x50 }, > + { 0xa4, 0x9c }, > + { 0xa7, 0x02 }, > + { 0xa8, 0x01 }, > + { 0xa9, 0x01 }, > + { 0xaa, 0xfc }, > + { 0xab, 0x28 }, > + { 0xac, 0x06 }, > + { 0xad, 0x06 }, > + { 0xae, 0x06 }, > + { 0xaf, 0x03 }, > + { 0xb0, 0x08 }, > + { 0xb1, 0x26 }, > + { 0xb2, 0x28 }, > + { 0xb3, 0x28 }, > + { 0xb4, 0x03 }, // Unknown, different to ltk035c5444 > + { 0xb5, 0x08 }, > + { 0xb6, 0x26 }, > + { 0xb7, 0x08 }, > + { 0xb8, 0x26 }, > + { 0xf0, 0x00 }, > + { 0xf6, 0xc0 }, > + // EXTC Command set enable, select page 0 > + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, > + // Set gray scale voltage to adjust gamma > + { 0xb0, 0x0b }, // PGAMVR0 > + { 0xb1, 0x16 }, // PGAMVR1 > + { 0xb2, 0x17 }, // PGAMVR2 > + { 0xb3, 0x2c }, // PGAMVR3 > + { 0xb4, 0x32 }, // PGAMVR4 > + { 0xb5, 0x3b }, // PGAMVR5 > + { 0xb6, 0x29 }, // PGAMPR0 > + { 0xb7, 0x40 }, // PGAMPR1 > + { 0xb8, 0x0d }, // PGAMPK0 > + { 0xb9, 0x05 }, // PGAMPK1 > + { 0xba, 0x12 }, // PGAMPK2 > + { 0xbb, 0x10 }, // PGAMPK3 > + { 0xbc, 0x12 }, // PGAMPK4 > + { 0xbd, 0x15 }, // PGAMPK5 > + { 0xbe, 0x19 }, // PGAMPK6 > + { 0xbf, 0x0e }, // PGAMPK7 > + { 0xc0, 0x16 }, // PGAMPK8 > + { 0xc1, 0x0a }, // PGAMPK9 > + // Set gray scale voltage to adjust gamma > + { 0xd0, 0x0c }, // NGAMVR0 > + { 0xd1, 0x17 }, // NGAMVR0 > + { 0xd2, 0x14 }, // NGAMVR1 > + { 0xd3, 0x2e }, // NGAMVR2 > + { 0xd4, 0x32 }, // NGAMVR3 > + { 0xd5, 0x3c }, // NGAMVR4 > + { 0xd6, 0x22 }, // NGAMPR0 > + { 0xd7, 0x3d }, // NGAMPR1 > + { 0xd8, 0x0d }, // NGAMPK0 > + { 0xd9, 0x07 }, // NGAMPK1 > + { 0xda, 0x13 }, // NGAMPK2 > + { 0xdb, 0x13 }, // NGAMPK3 > + { 0xdc, 0x11 }, // NGAMPK4 > + { 0xdd, 0x15 }, // NGAMPK5 > + { 0xde, 0x19 }, // NGAMPK6 > + { 0xdf, 0x10 }, // NGAMPK7 > + { 0xe0, 0x17 }, // NGAMPK8 > + { 0xe1, 0x0a }, // NGAMPK9 > + // EXTC Command set enable, select page 3 > + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, > + // Set various timing settings > + { 0x00, 0x2a }, // GIP_VST_1 > + { 0x01, 0x2a }, // GIP_VST_2 > + { 0x02, 0x2a }, // GIP_VST_3 > + { 0x03, 0x2a }, // GIP_VST_4 > + { 0x04, 0x61 }, // GIP_VST_5 > + { 0x05, 0x80 }, // GIP_VST_6 > + { 0x06, 0xc7 }, // GIP_VST_7 > + { 0x07, 0x01 }, // GIP_VST_8 > + { 0x08, 0x03 }, // GIP_VST_9 > + { 0x09, 0x04 }, // GIP_VST_10 > + { 0x70, 0x22 }, // GIP_ECLK1 > + { 0x71, 0x80 }, // GIP_ECLK2 > + { 0x30, 0x2a }, // GIP_CLK_1 > + { 0x31, 0x2a }, // GIP_CLK_2 > + { 0x32, 0x2a }, // GIP_CLK_3 > + { 0x33, 0x2a }, // GIP_CLK_4 > + { 0x34, 0x61 }, // GIP_CLK_5 > + { 0x35, 0xc5 }, // GIP_CLK_6 > + { 0x36, 0x80 }, // GIP_CLK_7 > + { 0x37, 0x23 }, // GIP_CLK_8 > + { 0x40, 0x03 }, // GIP_CLKA_1 > + { 0x41, 0x04 }, // GIP_CLKA_2 > + { 0x42, 0x05 }, // GIP_CLKA_3 > + { 0x43, 0x06 }, // GIP_CLKA_4 > + { 0x44, 0x11 }, // GIP_CLKA_5 > + { 0x45, 0xe8 }, // GIP_CLKA_6 > + { 0x46, 0xe9 }, // GIP_CLKA_7 > + { 0x47, 0x11 }, // GIP_CLKA_8 > + { 0x48, 0xea }, // GIP_CLKA_9 > + { 0x49, 0xeb }, // GIP_CLKA_10 > + { 0x50, 0x07 }, // GIP_CLKB_1 > + { 0x51, 0x08 }, // GIP_CLKB_2 > + { 0x52, 0x09 }, // GIP_CLKB_3 > + { 0x53, 0x0a }, // GIP_CLKB_4 > + { 0x54, 0x11 }, // GIP_CLKB_5 > + { 0x55, 0xec }, // GIP_CLKB_6 > + { 0x56, 0xed }, // GIP_CLKB_7 > + { 0x57, 0x11 }, // GIP_CLKB_8 > + { 0x58, 0xef }, // GIP_CLKB_9 > + { 0x59, 0xf0 }, // GIP_CLKB_10 > + // Map internal GOA signals to GOA output pad > + { 0xb1, 0x01 }, // PANELD2U2 > + { 0xb4, 0x15 }, // PANELD2U5 > + { 0xb5, 0x16 }, // PANELD2U6 > + { 0xb6, 0x09 }, // PANELD2U7 > + { 0xb7, 0x0f }, // PANELD2U8 > + { 0xb8, 0x0d }, // PANELD2U9 > + { 0xb9, 0x0b }, // PANELD2U10 > + { 0xba, 0x00 }, // PANELD2U11 > + { 0xc7, 0x02 }, // PANELD2U24 > + { 0xca, 0x17 }, // PANELD2U27 > + { 0xcb, 0x18 }, // PANELD2U28 > + { 0xcc, 0x0a }, // PANELD2U29 > + { 0xcd, 0x10 }, // PANELD2U30 > + { 0xce, 0x0e }, // PANELD2U31 > + { 0xcf, 0x0c }, // PANELD2U32 > + { 0xd0, 0x00 }, // PANELD2U33 > + // Map internal GOA signals to GOA output pad > + { 0x81, 0x00 }, // PANELU2D2 > + { 0x84, 0x15 }, // PANELU2D5 > + { 0x85, 0x16 }, // PANELU2D6 > + { 0x86, 0x10 }, // PANELU2D7 > + { 0x87, 0x0a }, // PANELU2D8 > + { 0x88, 0x0c }, // PANELU2D9 > + { 0x89, 0x0e }, // PANELU2D10 > + { 0x8a, 0x02 }, // PANELU2D11 > + { 0x97, 0x00 }, // PANELU2D24 > + { 0x9a, 0x17 }, // PANELU2D27 > + { 0x9b, 0x18 }, // PANELU2D28 > + { 0x9c, 0x0f }, // PANELU2D29 > + { 0x9d, 0x09 }, // PANELU2D30 > + { 0x9e, 0x0b }, // PANELU2D31 > + { 0x9f, 0x0d }, // PANELU2D32 > + { 0xa0, 0x01 }, // PANELU2D33 > + // EXTC Command set enable, select page 2 > + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, > + // Unknown registers > + { 0x01, 0x01 }, > + { 0x02, 0xda }, > + { 0x03, 0xba }, > + { 0x04, 0xa8 }, > + { 0x05, 0x9a }, > + { 0x06, 0x70 }, > + { 0x07, 0xff }, > + { 0x08, 0x91 }, > + { 0x09, 0x90 }, > + { 0x0a, 0xff }, > + { 0x0b, 0x8f }, > + { 0x0c, 0x60 }, > + { 0x0d, 0x58 }, > + { 0x0e, 0x48 }, > + { 0x0f, 0x38 }, > + { 0x10, 0x2b }, > + // EXTC Command set enable, select page 0 > + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, > + // Display Access Control > + { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 > +}; > + > static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) > { > return container_of(panel, struct nv3052c, panel); > @@ -463,6 +658,21 @@ static const struct drm_display_mode ltk035c5444t_modes[] = { > }, > }; > > +static const struct drm_display_mode fs035vg158_modes[] = { > + { /* 60 Hz */ > + .clock = 21000, > + .hdisplay = 640, > + .hsync_start = 640 + 34, > + .hsync_end = 640 + 34 + 4, > + .htotal = 640 + 34 + 4 + 20, > + .vdisplay = 480, > + .vsync_start = 480 + 12, > + .vsync_end = 480 + 12 + 4, > + .vtotal = 480 + 12 + 4 + 6, > + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, > + }, > +}; > + > static const struct nv3052c_panel_info ltk035c5444t_panel_info = { > .display_modes = ltk035c5444t_modes, > .num_modes = ARRAY_SIZE(ltk035c5444t_modes), > @@ -474,14 +684,27 @@ static const struct nv3052c_panel_info ltk035c5444t_panel_info = { > .panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs), > }; > > +static const struct nv3052c_panel_info fs035vg158_panel_info = { > + .display_modes = fs035vg158_modes, > + .num_modes = ARRAY_SIZE(fs035vg158_modes), > + .width_mm = 70, > + .height_mm = 53, > + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, > + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, > + .panel_regs = fs035vg158_panel_regs, > + .panel_regs_len = ARRAY_SIZE(fs035vg158_panel_regs), > +}; > + > static const struct spi_device_id nv3052c_ids[] = { > { "ltk035c5444t", }, > + { "fs035vg158", }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(spi, nv3052c_ids); > > static const struct of_device_id nv3052c_of_match[] = { > { .compatible = "leadtek,ltk035c5444t", .data = <k035c5444t_panel_info }, > + { .compatible = "fascontek,fs035vg158", .data = &fs035vg158_panel_info }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, nv3052c_of_match); > -- > 2.42.0 >
On Mon, Sep 18, 2023 at 01:19:03PM -0700, Jessica Zhang wrote: > Hi John, > > Just wondering, is there some context to this change? I.e., was this made to > fix a specific issue? > > This seems like a pretty significant increase in wait time so, if it's not a > fix, I'm not sure if this would be an improvement on the current behavior. > > Thanks, > > Jessica Zhang Hi Jessica, Thank you for the feedback. This patch here is required by the data sheet if the screen was already running and was reset. This is necessary if for example the bootloader set up and had the screen running. However I have not tested this, it's possible the specific panels have shorter tolerances for resets. This is purely precautionary at this stage based on what the data sheet says. That said I will be investigating this specific use case with this panel over the next few months. I am okay separating out this patch until I have proof it's needed for my particular display. I don't know anything about the ltk display. The second sleep patch can probably be omitted as I don't think the panel being prepared then unprepared in rapid succession is a realistic situation, but I figured I might as well propose it to see if it's the right thing to do. Thanks for your time and review, John.
Hi John, Le mardi 19 septembre 2023 à 06:52 +1000, John Watts a écrit : > On Mon, Sep 18, 2023 at 01:19:03PM -0700, Jessica Zhang wrote: > > Hi John, > > > > Just wondering, is there some context to this change? I.e., was > > this made to > > fix a specific issue? > > > > This seems like a pretty significant increase in wait time so, if > > it's not a > > fix, I'm not sure if this would be an improvement on the current > > behavior. > > > > Thanks, > > > > Jessica Zhang > > Hi Jessica, > > Thank you for the feedback. > > This patch here is required by the data sheet if the screen was > already running > and was reset. This is necessary if for example the bootloader set up > and had > the screen running. However I have not tested this, it's possible the > specific > panels have shorter tolerances for resets. This is purely > precautionary at > this stage based on what the data sheet says. > > That said I will be investigating this specific use case with this > panel over > the next few months. I am okay separating out this patch until I have > proof it's > needed for my particular display. I don't know anything about the ltk > display. > > The second sleep patch can probably be omitted as I don't think the > panel being > prepared then unprepared in rapid succession is a realistic > situation, but I > figured I might as well propose it to see if it's the right thing to > do. > > Thanks for your time and review, > John. The datasheet does say a 5ms sleep time is necesary after a reset. I assume the 120ms delay you quote is when a *software* reset is performed in Sleep-out mode. The code here does a hard-reset. Cheers, -Paul
On Mon, Sep 18, 2023 at 11:01:15PM +0200, Paul Cercueil wrote: > The datasheet does say a 5ms sleep time is necesary after a reset. I > assume the 120ms delay you quote is when a *software* reset is > performed in Sleep-out mode. The code here does a hard-reset. > > Cheers, > -Paul Hello Paul, Section 7.3 of the data sheet (AC characteristic) says that the reset can take up to 120ms to complete if the reset is applied during sleep out mode. John.
Le mardi 19 septembre 2023 à 07:08 +1000, John Watts a écrit : > On Mon, Sep 18, 2023 at 11:01:15PM +0200, Paul Cercueil wrote: > > The datasheet does say a 5ms sleep time is necesary after a reset. > > I > > assume the 120ms delay you quote is when a *software* reset is > > performed in Sleep-out mode. The code here does a hard-reset. > > > > Cheers, > > -Paul > > Hello Paul, > > Section 7.3 of the data sheet (AC characteristic) says that the reset > can take > up to 120ms to complete if the reset is applied during sleep out > mode. > > John. The driver is guaranteed to always reset the panel in sleep-in mode - as long as the panel was off when the driver started. What I'd suggest if you really need to support a case where the panel was enabled by the bootloader, is to read the 0x0a register after enabling the regulator to read the mode, and sleep 120ms if it was in sleep-out mode. But that's only if it's a case that you can test with. I won't accept a patch that makes sense on the surface if it addresses a corner case that nobody ever tested for. For what I know, this patch just adds a huge delay to panel boot-up for all existing users for no valid reason. Cheers, -Paul
On Mon, Sep 18, 2023 at 11:34:51PM +0200, Paul Cercueil wrote: > The driver is guaranteed to always reset the panel in sleep-in mode - > as long as the panel was off when the driver started. > > What I'd suggest if you really need to support a case where the panel > was enabled by the bootloader, is to read the 0x0a register after > enabling the regulator to read the mode, and sleep 120ms if it was in > sleep-out mode. > > But that's only if it's a case that you can test with. I won't accept a > patch that makes sense on the surface if it addresses a corner case > that nobody ever tested for. > > For what I know, this patch just adds a huge delay to panel boot-up for > all existing users for no valid reason. > > > Cheers, > -Paul Thank you very much for this feedback. I am more than happy to throw these sleep patches in the trash and come back later with a proper solution when I have an actual hardware setup and use case to test on. John.