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[0/3] pinctl: qcom: Add SM4450 pinctrl driver

Message ID 20230908063843.26835-1-quic_tengfan@quicinc.com
Headers show
Series pinctl: qcom: Add SM4450 pinctrl driver | expand

Message

Tengfei Fan Sept. 8, 2023, 6:38 a.m. UTC 
Add Sm4450 pinctrl driver for support enable uart console.

Tengfei Fan (3):
  dt-bindings: pinctrl: qcom: Add SM4450 pinctrl
  pinctrl: qcom: Add SM4450 pinctrl driver
  arm64: defconfig: Enable pinctrl for SM4450

 .../bindings/pinctrl/qcom,sm4450-tlmm.yaml    |  129 ++
 arch/arm64/configs/defconfig                  |    1 +
 drivers/pinctrl/qcom/Kconfig.msm              |    8 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-sm4450.c         | 1528 +++++++++++++++++
 5 files changed, 1667 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sm4450.c


base-commit: a47fc304d2b678db1a5d760a7d644dac9b067752

Comments

Konrad Dybcio Sept. 8, 2023, 8:45 a.m. UTC | #1 
On 8.09.2023 08:38, Tengfei Fan wrote:
> Add pinctrl driver for TLMM block found in SM4450 SoC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
[...]

> +/* Every pin is maintained as a single group, and missing or non-existing pin
/*
 * Every pin

> + * would be maintained as dummy group to synchronize pin group index with
> + * pin descriptor registered with pinctrl core.
> + * Clients would not be able to request these dummy pin groups.
> + */
[...]

> +static const int sm4450_acpi_reserved_gpios[] = {
> +	0, 1, 2, 3, 136, -1
> +};
Are you ever going to boot with ACPI on this platform?

Why reserve UFS_RESET?

Why are 0-3 reserved? FP reader? Please leave a comment. Or
delete this.

Konrad
Tengfei Fan Sept. 11, 2023, 1:23 a.m. UTC | #2 
在 9/8/2023 4:45 PM, Konrad Dybcio 写道:
> On 8.09.2023 08:38, Tengfei Fan wrote:
>> Add pinctrl driver for TLMM block found in SM4450 SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> [...]
> 
>> +/* Every pin is maintained as a single group, and missing or non-existing pin
> /*
>   * Every pin
> 
>> + * would be maintained as dummy group to synchronize pin group index with
>> + * pin descriptor registered with pinctrl core.
>> + * Clients would not be able to request these dummy pin groups.
>> + */
> [...]
> 
>> +static const int sm4450_acpi_reserved_gpios[] = {
>> +	0, 1, 2, 3, 136, -1
>> +};
> Are you ever going to boot with ACPI on this platform?
> 
> Why reserve UFS_RESET?
> 
> Why are 0-3 reserved? FP reader? Please leave a comment. Or
> delete this.
> 
> Konrad
Thanks Konrad reviewed this patch, will do more test and disscuss about 
this reserve gpio setting, and will remove this in next patch if possible.