mbox series

[00/31] Fix and improve Rockchip RK3128 support

Message ID 20230829171647.187787-1-knaerzche@gmail.com
Headers show
Series Fix and improve Rockchip RK3128 support | expand

Message

Alex Bee Aug. 29, 2023, 5:16 p.m. UTC
Hi list,

this series fixes some issues I found when testing my "new" RK3128 board
with the mainline kernel and adds some core functionality like SMP bringup,
usb and networking.

The propably most distinctive change is the split up of the DTs for the
different SoCs of this platform: RK3126 and RK3128. Even if I'm not adding
a RK3126 board in this series: I think this change should be done as early
as possible in order to avoid issues in future.
Actually it should have been done like that in the first place.

All patches have been tested on both SoCs:

Patch 01-04 are dt-bindings additions for this SoC platform and the new
board I'm addding here

Patch 05-07 are some clock driver fixes (there is more to do, but I'm
limiting it to the things which can work now)

Patch 08 and 09 adding support for the usb 2 phy found in RK312x platform
to the Rockchip Innosilicon usb phy driver.

Patch 10-14 are DT patches which I did in the "old" rk3128.dtsi in order
to be backportable.

Patch 15 does the aforementioned split-up of the current rk3128.dtsi in
rk312x.dtsi, rk3126.dtsi and rk3128.dtsi

Patch 16-20 adds SMP bringup and cpu frequency scaling

Patch 21-23 adds power controller, GPU and I2S nodes to the RK312x DT

Patch 24-26 adds the second I2S, S/PDIF and gmac nodes to the  RK3128 DT

Patch 27-30 adds fixes for the usb controllers and adds a missing
pincontrol for the sd card detection

Patch 31 finnaly adds a DT for Genatech XPI-3128 board

There are quite some HW blocks which can easily be added for this
platform, but I guess this series is pretty huge already, so that it is
limited to some core devices for now.
I hope the single patches are small enough, that reviewing won't be a
burden ;)

The plan is to sync the DT changes to u-boot after they are merged where
I'm planning to add "full" TPL/SPL for this platform (dram controller/phy
driver is currently missing)

I'm planing the add a RK3126 (tablet) board here as well, but I will have
to add support for RK816 pmic first.

Alex Bee (29):
  dt-bindings: mfd: syscon: Add rockchip,rk3128-qos compatible
  dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
  dt-bindings: ASoC: rockchip: Add compatible for RK3128 spdif
  dt-bindings: arm: rockchip: Add Geniatech XPI-3128
  clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
  phy: rockchip-inno-usb2: Split ID interrupt phy registers
  phy: phy-rockchip-inno-usb2: Add RK3128 support
  ARM: dts: rockchip: Fix i2c0 register address for RK3128
  ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
  ARM: dts: rockchip: Add missing quirk for RK3128's dma engine
  ARM: dts: rockchip: Fix timer clocks for RK3128
  ARM: dts: rockchip: Disable non-required timers for RK3128
  ARM: dts: rockchip: Split RK3128 devictree for RK312x SoC family
  ARM: dts: rockchip: Add SRAM node for RK312x
  ARM: dts: rockchip: Add CPU resets for RK312x
  ARM: dts: rockchip: Enable SMP bringup for RK312x
  ARM: dts: rockchip: Switch to operating-points-v2 for RK312x's CPU
  ARM: dts: rockchip: Add extra CPU voltages for RK3126
  ARM: dts: rockchip: add power controller for RK312x
  ARM: dts: rockchip: Add GPU node for RK312x
  ARM: dts: rockchip: Add 2-channel I2S for RK312x
  ARM: dts: rockchip: Add 8-channel I2S for RK3128
  ARM: dts: rockchip: Add spdif for RK3128
  ARM: dts: rockchip: Add gmac for RK3128
  ARM: dts: rockchip: Add dwc2 otg fifo siztes for RK312x
  ARM: dts: rockchip: Add USB host clocks for RK312x
  ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK312x
  ARM: dts: rockchip: Add sdmmc_det pinctrl for RK312x
  ARM: dts: Add Geniatech XPI-3128 RK3128 board

Finley Xiao (2):
  clk: rockchip: rk3128: Fix aclk_peri_src parent
  clk: rockchip: rk3128: Fix hclk_otg gate

 .../devicetree/bindings/arm/rockchip.yaml     |    5 +
 .../bindings/gpu/arm,mali-utgard.yaml         |    1 +
 .../devicetree/bindings/mfd/syscon.yaml       |    1 +
 .../bindings/sound/rockchip-spdif.yaml        |    1 +
 arch/arm/boot/dts/rockchip/Makefile           |    1 +
 arch/arm/boot/dts/rockchip/rk3126.dtsi        |   36 +
 .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts |  431 +++++++
 arch/arm/boot/dts/rockchip/rk3128.dtsi        |  920 +-------------
 arch/arm/boot/dts/rockchip/rk312x.dtsi        | 1101 +++++++++++++++++
 drivers/clk/rockchip/clk-rk3128.c             |   24 +-
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c |  147 ++-
 11 files changed, 1754 insertions(+), 914 deletions(-)
 create mode 100644 arch/arm/boot/dts/rockchip/rk3126.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
 create mode 100644 arch/arm/boot/dts/rockchip/rk312x.dtsi


base-commit: 2dde18cd1d8fac735875f2e4987f11817cc0bc2c

Comments

Krzysztof Kozlowski Aug. 29, 2023, 5:24 p.m. UTC | #1
On 29/08/2023 19:16, Alex Bee wrote:
> Currently there is only a SoC devicetree for RK3128 although RK312x
> SoC family consits of (at least) RK3126(C) and RK3128.
> 
> This splits up the currently existing rk3128.dtsi in rk312x.dtsi which
> contains the common definitions for both SoCs and rk3128.dtsi, rk3126.dtsi
> respectivly.

typos here and before

> 
> The differentiation between rk3126/rk3128 is already taken into account
> in the clock driver and they have their own compatibles.
> uart0 and i2c3 exist only in rk3128 SoC, thus they are moved to the new
> rk3128.dtsi.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  arch/arm/boot/dts/rockchip/rk3126.dtsi |   9 +
>  arch/arm/boot/dts/rockchip/rk3128.dtsi | 894 +------------------------
>  arch/arm/boot/dts/rockchip/rk312x.dtsi | 893 ++++++++++++++++++++++++

Please generate your patches with proper -M/-B/-C arguments to detect
the rename/copy.

>  3 files changed, 909 insertions(+), 887 deletions(-)
>  create mode 100644 arch/arm/boot/dts/rockchip/rk3126.dtsi
>  create mode 100644 arch/arm/boot/dts/rockchip/rk312x.dtsi
> 
> diff --git a/arch/arm/boot/dts/rockchip/rk3126.dtsi b/arch/arm/boot/dts/rockchip/rk3126.dtsi
> new file mode 100644
> index 000000000000..7345bd95d29d
> --- /dev/null
> +++ b/arch/arm/boot/dts/rockchip/rk3126.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +/dts-v1/;
> +
> +#include "rk312x.dtsi"
> +
> +/ {
> +	compatible = "rockchip,rk3126";
> +};
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index f3f0788195d2..4c5c9728179e 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -1,360 +1,11 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

This looks like relicensing, so without proper diff (see comment before)
it is a no-go.

>  
> -#include <dt-bindings/clock/rk3128-cru.h>
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -#include <dt-bindings/pinctrl/rockchip.h>
> +/dts-v1/;
> +
> +#include "rk312x.dtsi"
>  
>  / {
>  	compatible = "rockchip,rk3128";
> -	interrupt-parent = <&gic>;
> -	#address-cells = <1>;
> -	#size-cells = <1>;
> -
> -	arm-pmu {
> -		compatible = "arm,cortex-a7-pmu";
> -		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> -			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> -			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> -			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> -		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> -	};
> -
> -	cpus {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		cpu0: cpu@f00 {
> -			device_type = "cpu";
> -			compatible = "arm,cortex-a7";
> -			reg = <0xf00>;
> -			clock-latency = <40000>;
> -			clocks = <&cru ARMCLK>;
> -			operating-points = <
> -				/* KHz    uV */
> -				 816000 1000000
> -			>;
> -			#cooling-cells = <2>; /* min followed by max */
> -		};

All this patch is absolutely unreadable and unreviewable. Sorry, use the
tools to make review possible.



Best regards,
Krzysztof
Krzysztof Kozlowski Aug. 29, 2023, 5:25 p.m. UTC | #2
On 29/08/2023 19:16, Alex Bee wrote:
> RK312x SoCs have 8KB of SRAM.
> Add the respective device tree node for it.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---

This really does not depend on your MFD, GPU nor ASoC changes. Keep
independent work for different subsystems separate.

Best regards,
Krzysztof
Krzysztof Kozlowski Aug. 29, 2023, 5:25 p.m. UTC | #3
On 29/08/2023 19:16, Alex Bee wrote:
> Add the reset controls for all 4 cpu cores.

This we see from the diff. Commit should say why.


Best regards,
Krzysztof
Krzysztof Kozlowski Aug. 29, 2023, 5:40 p.m. UTC | #4
On 29/08/2023 19:16, Alex Bee wrote:
> From: Finley Xiao <finley.xiao@rock-chips.com>
> 
> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
> directly connects to the plls respectivly the pll divider clocks.
> Fix this by creating a single gated composite.
> 
> Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
> is the parent for both peri aclks and hclks and that also matches the
> naming in the TRM.
> 
> Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> [renamed aclk_peri_src -> clk_peri_src and added commit message]
> Signed-off-by: Alex Bee <knaerzche@gmail.com>

Please send fixes as separate patchset. Don't mix it with other work and
definitely it should not be in the middle of the patchset.

Best regards,
Krzysztof
Alex Bee Aug. 29, 2023, 6:36 p.m. UTC | #5
Hi Krzysztof,

thanks for your quick feedback.

You're right: This series mixes up too many things. I'll split up and 
re-send.

(And fix my typos, indeed)

Best Regards,

Alex

Am 29.08.23 um 19:40 schrieb Krzysztof Kozlowski:
> On 29/08/2023 19:16, Alex Bee wrote:
>> From: Finley Xiao <finley.xiao@rock-chips.com>
>>
>> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
>> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
>> directly connects to the plls respectivly the pll divider clocks.
>> Fix this by creating a single gated composite.
>>
>> Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
>> is the parent for both peri aclks and hclks and that also matches the
>> naming in the TRM.
>>
>> Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
>> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
>> [renamed aclk_peri_src -> clk_peri_src and added commit message]
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> Please send fixes as separate patchset. Don't mix it with other work and
> definitely it should not be in the middle of the patchset.
>
> Best regards,
> Krzysztof
>
Vinod Koul Sept. 21, 2023, 1:43 p.m. UTC | #6
On 29-08-23, 19:16, Alex Bee wrote:
> Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
> detection interrupt registers. However the current implementation assumes
> that falling and rising edge interrupt are always enabled in registers
> spaning over subsequent bits.
> That is not the case for RK312x's version of the phy and this
> implementation can't be used as-is, since there are bits with different
> purpose in between.
> 
> This splits up the register definitions for id_det_en, id_det_en and
> id_det_clr registers in rising and falling edge variants.
> It's required as preparation to support RK312x's Innosilicon usb2 phy as
> well in this driver and matches pretty much to what the vendor does, so I'm
> not expecting issues for other SoCs with that change.

This fails to apply for phy/next
Mark Brown Sept. 26, 2023, 8:08 a.m. UTC | #7
On Tue, 29 Aug 2023 19:16:16 +0200, Alex Bee wrote:
> this series fixes some issues I found when testing my "new" RK3128 board
> with the mainline kernel and adds some core functionality like SMP bringup,
> usb and networking.
> 
> The propably most distinctive change is the split up of the DTs for the
> different SoCs of this platform: RK3126 and RK3128. Even if I'm not adding
> a RK3126 board in this series: I think this change should be done as early
> as possible in order to avoid issues in future.
> Actually it should have been done like that in the first place.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[03/31] dt-bindings: ASoC: rockchip: Add compatible for RK3128 spdif
        commit: 5c8a033f5674ae62d5aa2ebbdb9980b89380c34f

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark
Vinod Koul Nov. 27, 2023, 1:22 p.m. UTC | #8
On Tue, 29 Aug 2023 19:16:16 +0200, Alex Bee wrote:
> this series fixes some issues I found when testing my "new" RK3128 board
> with the mainline kernel and adds some core functionality like SMP bringup,
> usb and networking.
> 
> The propably most distinctive change is the split up of the DTs for the
> different SoCs of this platform: RK3126 and RK3128. Even if I'm not adding
> a RK3126 board in this series: I think this change should be done as early
> as possible in order to avoid issues in future.
> Actually it should have been done like that in the first place.
> 
> [...]

Applied, thanks!

[08/31] phy: rockchip-inno-usb2: Split ID interrupt phy registers
        commit: 2fda59099462ee700e424ba3ac928d13ad6389a8
[09/31] phy: phy-rockchip-inno-usb2: Add RK3128 support
        commit: 62ff41017e147472b07de6125c3be82ce02a8dd7

Best regards,
Heiko Stübner Dec. 12, 2023, 8:03 p.m. UTC | #9
Hi Alex,

Am Dienstag, 29. August 2023, 19:16:16 CET schrieb Alex Bee:
> this series fixes some issues I found when testing my "new" RK3128 board
> with the mainline kernel and adds some core functionality like SMP bringup,
> usb and networking.

before I discard this thread, is everything from here migrated to
separate serieses or are there patches in this big pile that are still
relevant on their own, that haven't been applied?
[I lost track of what did go where ;-) ]


Thanks
Heiko
Alex Bee Dec. 13, 2023, 8:29 p.m. UTC | #10
Hi Heiko

Am 12.12.23 um 21:03 schrieb Heiko Stuebner:
> Hi Alex,
>
> Am Dienstag, 29. August 2023, 19:16:16 CET schrieb Alex Bee:
>> this series fixes some issues I found when testing my "new" RK3128 board
>> with the mainline kernel and adds some core functionality like SMP bringup,
>> usb and networking.
> before I discard this thread, is everything from here migrated to
> separate serieses or are there patches in this big pile that are still
> relevant on their own, that haven't been applied?
> [I lost track of what did go where ;-) ]

No worries - I kept track :)

Not everything is re-sent yet (sound nodes, RK3126/RK3128 split-up) but 
you can discard this and will re-send everything left in separate series 
(as I said [0])

[0] 
https://lore.kernel.org/linux-arm-kernel/170109134007.42627.12929766893521974712.b4-ty@kernel.org/T/#m63efa1c1379353b5cf764d2f9a260cf0329c864c

Regards,

Alex

>
>
> Thanks
> Heiko
>
>