| Message ID | 20230825093219.2685912-1-yoshihiro.shimoda.uh@renesas.com |
|---|---|
| Headers | show |
| Series | PCI: rcar-gen4: Add R-Car Gen4 PCIe support | expand |
On Fri, Aug 25, 2023 at 06:32:11PM +0900, Yoshihiro Shimoda wrote: > Since no PCIe controller drivers call this, this change is not required > for now. But, Renesas R-Car Gen4 PCIe controller driver will call this > and if the controller driver is built as a kernel module, the following > build error happens. So, expose dw_pcie_write_dbi2() for it. > > ERROR: modpost: "dw_pcie_write_dbi2" [drivers/pci/controller/dwc/pcie-rcar-gen4-host-drv.ko] undefined! > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> -Serge(y) > --- > drivers/pci/controller/dwc/pcie-designware.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 4812ce040f1e..0251fa1357f9 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -365,6 +365,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) > if (ret) > dev_err(pci->dev, "write DBI address failed\n"); > } > +EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); > > static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, > u32 index) > -- > 2.25.1 >
Hi Mani, Bjorn, Lorenzo, Krzysztof, Rob On Fri, Aug 25, 2023 at 06:32:00PM +0900, Yoshihiro Shimoda wrote: > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > To support them, modify PCIe DesignWare common codes. No more comments from my side for this series. It looks good to me now. If you have nothing to note too please merge it in especially seeing it's already v20.) -Serge(y) > > Changes from v19: > https://lore.kernel.org/linux-pci/20230823091153.2578417-1-yoshihiro.shimoda.uh@renesas.com/ > - Based on the latest pci.git / next branch and the following patches: > [PATCH v3 0/2] Cleanup IRQ type definitions > https://lore.kernel.org/linux-pci/20230802094036.1052472-1-dlemoal@kernel.org/ > - Rename PCI_MSG_TYPE_R_* macros in the patch 01/19. > - Fix the comment in the patch 04/19. > - Add Reviewed-by in the patch {06,1[2678]/19. > - Modify common functions for the same method of clock handling in the patch > 1[78]/19. > - Remove redundant gpio handling in the patch 16/19. > > Changes from v18: > https://lore.kernel.org/linux-pci/20230721074452.65545-1-yoshihiro.shimoda.uh@renesas.com/ > - Based on the latest pci.git / next branch and the following patches: > [PATCH v3 0/2] Cleanup IRQ type definitions > https://lore.kernel.org/linux-pci/20230802094036.1052472-1-dlemoal@kernel.org/ > - Drop some patches about converting "legacy" to "INTx". > - Add detailed description in the patch 0[26]/19. > - Add a new patch "Expose dw_pcie_write_dbi2" in the patch 11/19. > - Revise typo in the patch 12/19. > - Fix calling order of deinit in the patch 12/19. > - Revise Kconfig about kernel module names in the patch 1[67]/19. > - Rename drivers' file names in the patch 1[67]/19. > - Some other minor change/fix in the patch 1[67]/19. > > Yoshihiro Shimoda (19): > PCI: Add INTx Mechanism Messages macros > PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() > PCI: dwc: Add outbound MSG TLPs support > PCI: designware-ep: Add INTx IRQs support > PCI: dwc: endpoint: Add multiple PFs support for dbi2 > PCI: dwc: Add dw_pcie_link_set_max_link_width() > PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling > PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting > PCI: dwc: Add EDMA_UNROLL capability flag > PCI: dwc: Expose dw_pcie_ep_exit() to module > PCI: dwc: Expose dw_pcie_write_dbi2() to module > PCI: dwc: endpoint: Introduce .pre_init() and .deinit() > dt-bindings: PCI: dwc: Update maxItems of reg and reg-names > dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host > dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint > PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support > PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support > MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 > misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller > > .../bindings/pci/rcar-gen4-pci-ep.yaml | 106 ++++++++ > .../bindings/pci/rcar-gen4-pci-host.yaml | 123 ++++++++++ > .../bindings/pci/snps,dw-pcie-ep.yaml | 4 +- > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 4 +- > MAINTAINERS | 1 + > drivers/misc/pci_endpoint_test.c | 4 + > drivers/pci/controller/dwc/Kconfig | 20 ++ > drivers/pci/controller/dwc/Makefile | 4 + > .../pci/controller/dwc/pcie-designware-ep.c | 136 +++++++++-- > .../pci/controller/dwc/pcie-designware-host.c | 52 ++-- > drivers/pci/controller/dwc/pcie-designware.c | 156 ++++++------ > drivers/pci/controller/dwc/pcie-designware.h | 29 ++- > .../controller/dwc/pcie-rcar-gen4-ep-drv.c | 173 +++++++++++++ > .../controller/dwc/pcie-rcar-gen4-host-drv.c | 135 +++++++++++ > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 227 ++++++++++++++++++ > drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++ > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > drivers/pci/pci.h | 18 ++ > 18 files changed, 1111 insertions(+), 131 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep-drv.c > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host-drv.c > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h > > -- > 2.25.1 >
Hello everyone! > > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > > To support them, modify PCIe DesignWare common codes. > > No more comments from my side for this series. It looks good to me > now. If you have nothing to note too please merge it in especially > seeing it's already v20.) Yes, it's about time we pull it. Thank you everyone involved in the work here, especially reviews (Sergey and Manivannan), as the series looks amazing. That said, some patches in the series do not apply cleanly against 6.5-rc1, so I need to have a closer look a little bit later, hopefully I will be able to get it in time before Bjorn sends his Pull Request. シモダさん、 一連のシリーズお疲れ様でした！ 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ Thank you! Krzysztof
Hello, > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > To support them, modify PCIe DesignWare common codes. Applied to controller/rcar, thank you! [01/19] PCI: Add INTx Mechanism Messages macros https://git.kernel.org/pci/pci/c/b6dc5750a17a [02/19] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() https://git.kernel.org/pci/pci/c/6cbd4d406cb0 [03/19] PCI: dwc: Add outbound MSG TLPs support https://git.kernel.org/pci/pci/c/6ab660b25520 [04/19] PCI: designware-ep: Add INTx IRQs support https://git.kernel.org/pci/pci/c/b788d6fd273e [05/19] PCI: dwc: endpoint: Add multiple PFs support for dbi2 https://git.kernel.org/pci/pci/c/6e4db9846cf4 [06/19] PCI: dwc: Add dw_pcie_link_set_max_link_width() https://git.kernel.org/pci/pci/c/d0f961f40da8 [07/19] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling https://git.kernel.org/pci/pci/c/a0473c77b4c1 [08/19] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting https://git.kernel.org/pci/pci/c/e45ff874cede [09/19] PCI: dwc: Add EDMA_UNROLL capability flag https://git.kernel.org/pci/pci/c/2424c3ddbd4c [10/19] PCI: dwc: Expose dw_pcie_ep_exit() to module https://git.kernel.org/pci/pci/c/3f937c80eb8e [11/19] PCI: dwc: Expose dw_pcie_write_dbi2() to module https://git.kernel.org/pci/pci/c/a986f6fd339e [12/19] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() https://git.kernel.org/pci/pci/c/6504d294399e [13/19] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names https://git.kernel.org/pci/pci/c/5ca157f7d36c [14/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host https://git.kernel.org/pci/pci/c/af285bc39885 [15/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint https://git.kernel.org/pci/pci/c/738bded11aaa [16/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support https://git.kernel.org/pci/pci/c/943a310da907 [17/19] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support https://git.kernel.org/pci/pci/c/db4499d11f46 [18/19] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 https://git.kernel.org/pci/pci/c/2e0ef5776946 [19/19] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller https://git.kernel.org/pci/pci/c/33fa67818fe7 Krzysztof
Hello Krzysztof, Serge, Manivannan, > From: Krzysztof Wilczyński, Sent: Sunday, August 27, 2023 3:59 PM > > Hello everyone! > > > > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > > > To support them, modify PCIe DesignWare common codes. > > > > No more comments from my side for this series. It looks good to me > > now. If you have nothing to note too please merge it in especially > > seeing it's already v20.) > > Yes, it's about time we pull it. Thank you everyone involved in the work > here, especially reviews (Sergey and Manivannan), as the series looks > amazing. Thank you very much for your support! > That said, some patches in the series do not apply cleanly against 6.5-rc1, > so I need to have a closer look a little bit later, hopefully I will be > able to get it in time before Bjorn sends his Pull Request. I'm sorry for bothering you about the conflict because my patch set is based on pci.git / next, not 6.5-rc1... But, anyway, thank you for applying to controller/rcar! > シモダさん、 > > 一連のシリーズお疲れ様でした！ > 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました > 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 > ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ Thank you for your comment in Japanese! こちらこそ、ありがとうございました！ Best regards, Yoshihiro Shimoda > Thank you! > > Krzysztof
On Mon, Aug 28, 2023 at 01:19:17AM +0000, Yoshihiro Shimoda wrote: > Hello Krzysztof, Serge, Manivannan, > > > From: Krzysztof Wilczyński, Sent: Sunday, August 27, 2023 3:59 PM > > > > Hello everyone! > > > > > > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > > > > To support them, modify PCIe DesignWare common codes. > > > > > > No more comments from my side for this series. It looks good to me > > > now. If you have nothing to note too please merge it in especially > > > seeing it's already v20.) > > > > Yes, it's about time we pull it. Thank you everyone involved in the work > > here, especially reviews (Sergey and Manivannan), as the series looks > > amazing. > > Thank you very much for your support! > Thanks for your patience and perseverance! And thanks a lot Sergey for helping with the review. - Mani > > That said, some patches in the series do not apply cleanly against 6.5-rc1, > > so I need to have a closer look a little bit later, hopefully I will be > > able to get it in time before Bjorn sends his Pull Request. > > I'm sorry for bothering you about the conflict because my patch set is based on pci.git / next, > not 6.5-rc1... But, anyway, thank you for applying to controller/rcar! > > > シモダさん、 > > > > 一連のシリーズお疲れ様でした！ > > 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました > > 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 > > ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ > > Thank you for your comment in Japanese! > こちらこそ、ありがとうございました！ > > Best regards, > Yoshihiro Shimoda > > > Thank you! > > > > Krzysztof
Hi Yoshihiro, On Mon, Aug 28, 2023 at 01:19:17AM +0000, Yoshihiro Shimoda wrote: > Hello Krzysztof, Serge, Manivannan, > > > From: Krzysztof Wilczyński, Sent: Sunday, August 27, 2023 3:59 PM > > > > Hello everyone! > > > > > > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > > > > To support them, modify PCIe DesignWare common codes. > > > > > > No more comments from my side for this series. It looks good to me > > > now. If you have nothing to note too please merge it in especially > > > seeing it's already v20.) > > > > Yes, it's about time we pull it. Thank you everyone involved in the work > > here, especially reviews (Sergey and Manivannan), as the series looks > > amazing. > > Thank you very much for your support! It was my pleasure to be reviewing your patchset. Thanks you very much for the patience and strong eagerness to complete the turned out to be such a long-time procedure. I'm sorry if sometimes I acted too meticulous.) It was always done from out of reaching greater good. Regards -Serge(y) > > > That said, some patches in the series do not apply cleanly against 6.5-rc1, > > so I need to have a closer look a little bit later, hopefully I will be > > able to get it in time before Bjorn sends his Pull Request. > > I'm sorry for bothering you about the conflict because my patch set is based on pci.git / next, > not 6.5-rc1... But, anyway, thank you for applying to controller/rcar! > > > シモダさん、 > > > > 一連のシリーズお疲れ様でした！ > > 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました > > 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 > > ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ > > Thank you for your comment in Japanese! > こちらこそ、ありがとうございました！ > > Best regards, > Yoshihiro Shimoda > > > Thank you! > > > > Krzysztof
Hello, [...] > > That said, some patches in the series do not apply cleanly against 6.5-rc1, > > so I need to have a closer look a little bit later, hopefully I will be > > able to get it in time before Bjorn sends his Pull Request. > > I'm sorry for bothering you about the conflict because my patch set is based on pci.git / next, > not 6.5-rc1... But, anyway, thank you for applying to controller/rcar! No problem! That said, it's always a good idea to check the main branch from the following the repository to see which version to work against if possible. PCI development lives at: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git > > シモダさん、 > > > > 一連のシリーズお疲れ様でした！ > > 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました > > 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 > > ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ > > Thank you for your comment in Japanese! > こちらこそ、ありがとうございました！ Sure thing! Greetings from Yokohama. :) Krzysztof
Hi Serge, > From: Serge Semin, Sent: Monday, August 28, 2023 10:58 PM > > Hi Yoshihiro, > > On Mon, Aug 28, 2023 at 01:19:17AM +0000, Yoshihiro Shimoda wrote: > > Hello Krzysztof, Serge, Manivannan, > > > > > From: Krzysztof Wilczyński, Sent: Sunday, August 27, 2023 3:59 PM > > > > > > Hello everyone! > > > > > > > > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > > > > > To support them, modify PCIe DesignWare common codes. > > > > > > > > No more comments from my side for this series. It looks good to me > > > > now. If you have nothing to note too please merge it in especially > > > > seeing it's already v20.) > > > > > > Yes, it's about time we pull it. Thank you everyone involved in the work > > > here, especially reviews (Sergey and Manivannan), as the series looks > > > amazing. > > > > Thank you very much for your support! > > It was my pleasure to be reviewing your patchset. Thanks you very much > for the patience and strong eagerness to complete the turned out to be > such a long-time procedure. I'm sorry if sometimes I acted too > meticulous.) It was always done from out of reaching greater good. I appreciate your support. My patch set became quite better by your kindly review! Best regards, Yoshihiro Shimoda > Regards > -Serge(y) > > > > > > That said, some patches in the series do not apply cleanly against 6.5-rc1, > > > so I need to have a closer look a little bit later, hopefully I will be > > > able to get it in time before Bjorn sends his Pull Request. > > > > I'm sorry for bothering you about the conflict because my patch set is based on pci.git / next, > > not 6.5-rc1... But, anyway, thank you for applying to controller/rcar! > > > > > シモダさん、 > > > > > > 一連のシリーズお疲れ様でした！ > > > 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました > > > 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 > > > ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ > > > > Thank you for your comment in Japanese! > > こちらこそ、ありがとうございました！ > > > > Best regards, > > Yoshihiro Shimoda > > > > > Thank you! > > > > > > Krzysztof
Hello Krzysztof, > From: Krzysztof Wilczyński, Sent: Tuesday, August 29, 2023 1:07 AM > > Hello, > > [...] > > > That said, some patches in the series do not apply cleanly against 6.5-rc1, > > > so I need to have a closer look a little bit later, hopefully I will be > > > able to get it in time before Bjorn sends his Pull Request. > > > > I'm sorry for bothering you about the conflict because my patch set is based on pci.git / next, > > not 6.5-rc1... But, anyway, thank you for applying to controller/rcar! > > No problem! > > That said, it's always a good idea to check the main branch from the > following the repository to see which version to work against if > possible. PCI development lives at: > > https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git I checked that v6.5-rc1 + controller/rcar + the following dtsi/dts patches I have submitted [1] worked correctly. Thank you for your support! [1] https://lore.kernel.org/all/20230828041434.2747699-1-yoshihiro.shimoda.uh@renesas.com/ > > > シモダさん、 > > > > > > 一連のシリーズお疲れ様でした！ > > > 特に、作業が少し前に開始され、レビューされるまでに時間がかかった点お手数をおかけいたしました > > > 全ての要求変更の追加にご協力いただき、ありがとうございます。 個人的にも本当に有難いです。 > > > ご担当いただいた仕事は素晴らしいものでした。 重ねてにはなりますが、どうもありがとう！ > > > > Thank you for your comment in Japanese! > > こちらこそ、ありがとうございました！ > > Sure thing! Greetings from Yokohama. :) Oh! Yokohama! It's a nice city :) Best regards, Yoshihiro Shimoda > Krzysztof
Hello Bjorn, > From: Krzysztof Wilczyński, Sent: Monday, August 28, 2023 1:27 AM > > Hello, > > > Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. > > To support them, modify PCIe DesignWare common codes. > > Applied to controller/rcar, thank you! I should have asked you before, but is it possible to merge this for Linux v6.6? Today I realized that "[GIT PULL] PCI changes for v6.6" [1] didn't have the controller/rcar... [1] https://lore.kernel.org/linux-pci/20230830190642.GA10547@bhelgaas/ Best regards, Yoshihiro Shimoda > [01/19] PCI: Add INTx Mechanism Messages macros > https://git.kernel.org/pci/pci/c/b6dc5750a17a > [02/19] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() > https://git.kernel.org/pci/pci/c/6cbd4d406cb0 > [03/19] PCI: dwc: Add outbound MSG TLPs support > https://git.kernel.org/pci/pci/c/6ab660b25520 > [04/19] PCI: designware-ep: Add INTx IRQs support > https://git.kernel.org/pci/pci/c/b788d6fd273e > [05/19] PCI: dwc: endpoint: Add multiple PFs support for dbi2 > https://git.kernel.org/pci/pci/c/6e4db9846cf4 > [06/19] PCI: dwc: Add dw_pcie_link_set_max_link_width() > https://git.kernel.org/pci/pci/c/d0f961f40da8 > [07/19] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling > https://git.kernel.org/pci/pci/c/a0473c77b4c1 > [08/19] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting > https://git.kernel.org/pci/pci/c/e45ff874cede > [09/19] PCI: dwc: Add EDMA_UNROLL capability flag > https://git.kernel.org/pci/pci/c/2424c3ddbd4c > [10/19] PCI: dwc: Expose dw_pcie_ep_exit() to module > https://git.kernel.org/pci/pci/c/3f937c80eb8e > [11/19] PCI: dwc: Expose dw_pcie_write_dbi2() to module > https://git.kernel.org/pci/pci/c/a986f6fd339e > [12/19] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() > https://git.kernel.org/pci/pci/c/6504d294399e > [13/19] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names > https://git.kernel.org/pci/pci/c/5ca157f7d36c > [14/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host > https://git.kernel.org/pci/pci/c/af285bc39885 > [15/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint > https://git.kernel.org/pci/pci/c/738bded11aaa > [16/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support > https://git.kernel.org/pci/pci/c/943a310da907 > [17/19] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support > https://git.kernel.org/pci/pci/c/db4499d11f46 > [18/19] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 > https://git.kernel.org/pci/pci/c/2e0ef5776946 > [19/19] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller > https://git.kernel.org/pci/pci/c/33fa67818fe7 > > Krzysztof
Hello, [...] > > Applied to controller/rcar, thank you! > > I should have asked you before, but is it possible to merge this for Linux v6.6? > Today I realized that "[GIT PULL] PCI changes for v6.6" [1] didn't have the controller/rcar... Bjorn chosen not to include the series as the scope of the changes also spans across the DWC code base, not only adding a new driver, and he wanted for it to remain a little bit longer on the -next, so that if there are issues, we can catch things... ... like the dt-bindings issues that Geert is asking about. That said, there will be no need to send an entire series again, if you have anything to fix there in the dt-bindings or the dts patches, and just send a new patches for these - I will pull and squash everything later. We are getting there. :) Krzysztof
Hello Krzysztof, > From: Krzysztof Wilczyński, Sent: Thursday, August 31, 2023 11:04 PM > > Hello, > > [...] > > > Applied to controller/rcar, thank you! > > > > I should have asked you before, but is it possible to merge this for Linux v6.6? > > Today I realized that "[GIT PULL] PCI changes for v6.6" [1] didn't have the controller/rcar... > > Bjorn chosen not to include the series as the scope of the changes also > spans across the DWC code base, not only adding a new driver, and he wanted > for it to remain a little bit longer on the -next, so that if there are > issues, we can catch things... > > ... like the dt-bindings issues that Geert is asking about. I got it. > That said, there will be no need to send an entire series again, if you > have anything to fix there in the dt-bindings or the dts patches, and just > send a new patches for these - I will pull and squash everything later. Thank you for explanation about how to fix it. I'll submit new patches for these. Best regards, Yoshihiro Shimoda > We are getting there. :) > > Krzysztof
On Fri, Aug 25, 2023 at 06:32:02PM +0900, Yoshihiro Shimoda wrote: > This is a preparation before adding the Msg-type outbound iATU > mapping. The respective update will require two more arguments added > to __dw_pcie_prog_outbound_atu(). That will make the already > complicated function prototype even more hard to comprehend accepting > _eight_ arguments. In order to prevent that and keep the code > more-or-less readable all the outbound iATU-related arguments are > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure > is supposed to be locally defined and populated with the outbound iATU > settings implied by the caller context. > > As a result of the denoted change there is no longer need in having > the two distinctive methods for the Host and End-point outbound iATU > setups since the corresponding code can directly call the > dw_pcie_prog_outbound_atu() method with the config-structure > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Yoshihiro: I want to use this patch to send out PME message when suspend, which should be similar with raise INTx. Can I include your this patches in my PME enable patches list if your patch still not merge yet. Frank > --- > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++--- > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------ > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++----------- > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++-- > 4 files changed, 77 insertions(+), 60 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index ab87ea3b0986..747d5bc07222 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, > return 0; > } > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, > - phys_addr_t phys_addr, > - u64 pci_addr, size_t size) > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, > + struct dw_pcie_ob_atu_cfg *atu) > { > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > u32 free_win; > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, > return -EINVAL; > } > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, > - phys_addr, pci_addr, size); > + atu->index = free_win; > + ret = dw_pcie_prog_outbound_atu(pci, atu); > if (ret) > return ret; > > set_bit(free_win, ep->ob_window_map); > - ep->outbound_addr[free_win] = phys_addr; > + ep->outbound_addr[free_win] = atu->cpu_addr; > > return 0; > } > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, > int ret; > struct dw_pcie_ep *ep = epc_get_drvdata(epc); > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > - > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > + > + atu.func_no = func_no; > + atu.type = PCIE_ATU_TYPE_MEM; > + atu.cpu_addr = addr; > + atu.pci_addr = pci_addr; > + atu.size = size; > + ret = dw_pcie_ep_outbound_atu(ep, &atu); > if (ret) { > dev_err(pci->dev, "Failed to enable address\n"); > return ret; > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 5c8cbc3afae4..01eff83c1f6d 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -551,6 +551,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, > { > struct dw_pcie_rp *pp = bus->sysdata; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > int type, ret; > u32 busdev; > > @@ -573,8 +574,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, > else > type = PCIE_ATU_TYPE_CFG1; > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, > - pp->cfg0_size); > + atu.type = type; > + atu.cpu_addr = pp->cfg0_base; > + atu.pci_addr = busdev; > + atu.size = pp->cfg0_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) > return NULL; > > @@ -586,6 +591,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, > { > struct dw_pcie_rp *pp = bus->sysdata; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > int ret; > > ret = pci_generic_config_read(bus, devfn, where, size, val); > @@ -593,9 +599,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, > return ret; > > if (pp->cfg0_io_shared) { > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, > - pp->io_base, pp->io_bus_addr, > - pp->io_size); > + atu.type = PCIE_ATU_TYPE_IO; > + atu.cpu_addr = pp->io_base; > + atu.pci_addr = pp->io_bus_addr; > + atu.size = pp->io_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) > return PCIBIOS_SET_FAILED; > } > @@ -608,6 +617,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, > { > struct dw_pcie_rp *pp = bus->sysdata; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > int ret; > > ret = pci_generic_config_write(bus, devfn, where, size, val); > @@ -615,9 +625,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, > return ret; > > if (pp->cfg0_io_shared) { > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, > - pp->io_base, pp->io_bus_addr, > - pp->io_size); > + atu.type = PCIE_ATU_TYPE_IO; > + atu.cpu_addr = pp->io_base; > + atu.pci_addr = pp->io_bus_addr; > + atu.size = pp->io_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) > return PCIBIOS_SET_FAILED; > } > @@ -652,6 +665,7 @@ static struct pci_ops dw_pcie_ops = { > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > struct resource_entry *entry; > int i, ret; > > @@ -679,10 +693,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > if (pci->num_ob_windows <= ++i) > break; > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, > - entry->res->start, > - entry->res->start - entry->offset, > - resource_size(entry->res)); > + atu.index = i; > + atu.type = PCIE_ATU_TYPE_MEM; > + atu.cpu_addr = entry->res->start; > + atu.pci_addr = entry->res->start - entry->offset; > + atu.size = resource_size(entry->res); > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) { > dev_err(pci->dev, "Failed to set MEM range %pr\n", > entry->res); > @@ -692,10 +709,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > if (pp->io_size) { > if (pci->num_ob_windows > ++i) { > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, > - pp->io_base, > - pp->io_bus_addr, > - pp->io_size); > + atu.index = i; > + atu.type = PCIE_ATU_TYPE_IO; > + atu.cpu_addr = pp->io_base; > + atu.pci_addr = pp->io_bus_addr; > + atu.size = pp->io_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) { > dev_err(pci->dev, "Failed to set IO range %pr\n", > entry->res); > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 2459f2a61b9b..49b785509576 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val) > return val | PCIE_ATU_TD; > } > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, > - int index, int type, u64 cpu_addr, > - u64 pci_addr, u64 size) > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > + const struct dw_pcie_ob_atu_cfg *atu) > { > + u64 cpu_addr = atu->cpu_addr; > u32 retries, val; > u64 limit_addr; > > if (pci->ops && pci->ops->cpu_addr_fixup) > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); > > - limit_addr = cpu_addr + size - 1; > + limit_addr = cpu_addr + atu->size - 1; > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || > !IS_ALIGNED(cpu_addr, pci->region_align) || > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) { > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { > return -EINVAL; > } > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, > lower_32_bits(cpu_addr)); > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, > upper_32_bits(cpu_addr)); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, > lower_32_bits(limit_addr)); > if (dw_pcie_ver_is_ge(pci, 460A)) > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, > upper_32_bits(limit_addr)); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET, > - lower_32_bits(pci_addr)); > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET, > - upper_32_bits(pci_addr)); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, > + lower_32_bits(atu->pci_addr)); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, > + upper_32_bits(atu->pci_addr)); > > - val = type | PCIE_ATU_FUNC_NUM(func_no); > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && > dw_pcie_ver_is_ge(pci, 460A)) > val |= PCIE_ATU_INCREASE_REGION_SIZE; > if (dw_pcie_ver_is(pci, 490A)) > val = dw_pcie_enable_ecrc(val); > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); > > /* > * Make sure ATU enable takes effect before any subsequent config > * and I/O accesses. > */ > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2); > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); > if (val & PCIE_ATU_ENABLE) > return 0; > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, > return -ETIMEDOUT; > } > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, > - u64 cpu_addr, u64 pci_addr, u64 size) > -{ > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type, > - cpu_addr, pci_addr, size); > -} > - > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, > - int type, u64 cpu_addr, u64 pci_addr, > - u64 size) > -{ > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type, > - cpu_addr, pci_addr, size); > -} > - > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) > { > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 755bcb406769..296c5b1ddc91 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -298,6 +298,15 @@ enum dw_pcie_ltssm { > DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, > }; > > +struct dw_pcie_ob_atu_cfg { > + int index; > + int type; > + u8 func_no; > + u64 cpu_addr; > + u64 pci_addr; > + u64 size; > +}; > + > struct dw_pcie_host_ops { > int (*host_init)(struct dw_pcie_rp *pp); > void (*host_deinit)(struct dw_pcie_rp *pp); > @@ -429,10 +438,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); > int dw_pcie_link_up(struct dw_pcie *pci); > void dw_pcie_upconfig_setup(struct dw_pcie *pci); > int dw_pcie_wait_for_link(struct dw_pcie *pci); > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, > - u64 cpu_addr, u64 pci_addr, u64 size); > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, > - int type, u64 cpu_addr, u64 pci_addr, u64 size); > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > + const struct dw_pcie_ob_atu_cfg *atu); > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, > u64 cpu_addr, u64 pci_addr, u64 size); > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, > -- > 2.25.1 >
> From: Frank Li, Sent: Tuesday, January 30, 2024 7:42 AM > > On Fri, Aug 25, 2023 at 06:32:02PM +0900, Yoshihiro Shimoda wrote: > > This is a preparation before adding the Msg-type outbound iATU > > mapping. The respective update will require two more arguments added > > to __dw_pcie_prog_outbound_atu(). That will make the already > > complicated function prototype even more hard to comprehend accepting > > _eight_ arguments. In order to prevent that and keep the code > > more-or-less readable all the outbound iATU-related arguments are > > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer > > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure > > is supposed to be locally defined and populated with the outbound iATU > > settings implied by the caller context. > > > > As a result of the denoted change there is no longer need in having > > the two distinctive methods for the Host and End-point outbound iATU > > setups since the corresponding code can directly call the > > dw_pcie_prog_outbound_atu() method with the config-structure > > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Yoshihiro: > > I want to use this patch to send out PME message when suspend, > which should be similar with raise INTx. Can I include your this patches in > my PME enable patches list if your patch still not merge yet. Sure! This patch is not merged yet because INTx support requires framework modification and this INTx support is not mandatory for my environment [1]. [1] https://lore.kernel.org/all/TYBPR01MB534141F4F7B419BFE473D9B5D8FAA@TYBPR01MB5341.jpnprd01.prod.outlook.com/ Best regards, Yoshihiro Shimoda > Frank > > > --- > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++--- > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------ > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++----------- > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++-- > > 4 files changed, 77 insertions(+), 60 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > > index ab87ea3b0986..747d5bc07222 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, > > return 0; > > } > > > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, > > - phys_addr_t phys_addr, > > - u64 pci_addr, size_t size) > > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, > > + struct dw_pcie_ob_atu_cfg *atu) > > { > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > u32 free_win; > > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, > > return -EINVAL; > > } > > > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, > > - phys_addr, pci_addr, size); > > + atu->index = free_win; > > + ret = dw_pcie_prog_outbound_atu(pci, atu); > > if (ret) > > return ret; > > > > set_bit(free_win, ep->ob_window_map); > > - ep->outbound_addr[free_win] = phys_addr; > > + ep->outbound_addr[free_win] = atu->cpu_addr; > > > > return 0; > > } > > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, > > int ret; > > struct dw_pcie_ep *ep = epc_get_drvdata(epc); > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > - > > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); > > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > > + > > + atu.func_no = func_no; > > + atu.type = PCIE_ATU_TYPE_MEM; > > + atu.cpu_addr = addr; > > + atu.pci_addr = pci_addr; > > + atu.size = size; > > + ret = dw_pcie_ep_outbound_atu(ep, &atu); > > if (ret) { > > dev_err(pci->dev, "Failed to enable address\n"); > > return ret; > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > > index 5c8cbc3afae4..01eff83c1f6d 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > @@ -551,6 +551,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, > > { > > struct dw_pcie_rp *pp = bus->sysdata; > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > > int type, ret; > > u32 busdev; > > > > @@ -573,8 +574,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, > > else > > type = PCIE_ATU_TYPE_CFG1; > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, > > - pp->cfg0_size); > > + atu.type = type; > > + atu.cpu_addr = pp->cfg0_base; > > + atu.pci_addr = busdev; > > + atu.size = pp->cfg0_size; > > + > > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > > if (ret) > > return NULL; > > > > @@ -586,6 +591,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, > > { > > struct dw_pcie_rp *pp = bus->sysdata; > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > > int ret; > > > > ret = pci_generic_config_read(bus, devfn, where, size, val); > > @@ -593,9 +599,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, > > return ret; > > > > if (pp->cfg0_io_shared) { > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, > > - pp->io_base, pp->io_bus_addr, > > - pp->io_size); > > + atu.type = PCIE_ATU_TYPE_IO; > > + atu.cpu_addr = pp->io_base; > > + atu.pci_addr = pp->io_bus_addr; > > + atu.size = pp->io_size; > > + > > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > > if (ret) > > return PCIBIOS_SET_FAILED; > > } > > @@ -608,6 +617,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, > > { > > struct dw_pcie_rp *pp = bus->sysdata; > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > > int ret; > > > > ret = pci_generic_config_write(bus, devfn, where, size, val); > > @@ -615,9 +625,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, > > return ret; > > > > if (pp->cfg0_io_shared) { > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, > > - pp->io_base, pp->io_bus_addr, > > - pp->io_size); > > + atu.type = PCIE_ATU_TYPE_IO; > > + atu.cpu_addr = pp->io_base; > > + atu.pci_addr = pp->io_bus_addr; > > + atu.size = pp->io_size; > > + > > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > > if (ret) > > return PCIBIOS_SET_FAILED; > > } > > @@ -652,6 +665,7 @@ static struct pci_ops dw_pcie_ops = { > > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > { > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > > struct resource_entry *entry; > > int i, ret; > > > > @@ -679,10 +693,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > if (pci->num_ob_windows <= ++i) > > break; > > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, > > - entry->res->start, > > - entry->res->start - entry->offset, > > - resource_size(entry->res)); > > + atu.index = i; > > + atu.type = PCIE_ATU_TYPE_MEM; > > + atu.cpu_addr = entry->res->start; > > + atu.pci_addr = entry->res->start - entry->offset; > > + atu.size = resource_size(entry->res); > > + > > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > > if (ret) { > > dev_err(pci->dev, "Failed to set MEM range %pr\n", > > entry->res); > > @@ -692,10 +709,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > > > if (pp->io_size) { > > if (pci->num_ob_windows > ++i) { > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, > > - pp->io_base, > > - pp->io_bus_addr, > > - pp->io_size); > > + atu.index = i; > > + atu.type = PCIE_ATU_TYPE_IO; > > + atu.cpu_addr = pp->io_base; > > + atu.pci_addr = pp->io_bus_addr; > > + atu.size = pp->io_size; > > + > > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > > if (ret) { > > dev_err(pci->dev, "Failed to set IO range %pr\n", > > entry->res); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 2459f2a61b9b..49b785509576 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val) > > return val | PCIE_ATU_TD; > > } > > > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, > > - int index, int type, u64 cpu_addr, > > - u64 pci_addr, u64 size) > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > > + const struct dw_pcie_ob_atu_cfg *atu) > > { > > + u64 cpu_addr = atu->cpu_addr; > > u32 retries, val; > > u64 limit_addr; > > > > if (pci->ops && pci->ops->cpu_addr_fixup) > > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); > > > > - limit_addr = cpu_addr + size - 1; > > + limit_addr = cpu_addr + atu->size - 1; > > > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || > > !IS_ALIGNED(cpu_addr, pci->region_align) || > > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) { > > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { > > return -EINVAL; > > } > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE, > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, > > lower_32_bits(cpu_addr)); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE, > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, > > upper_32_bits(cpu_addr)); > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT, > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, > > lower_32_bits(limit_addr)); > > if (dw_pcie_ver_is_ge(pci, 460A)) > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT, > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, > > upper_32_bits(limit_addr)); > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET, > > - lower_32_bits(pci_addr)); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET, > > - upper_32_bits(pci_addr)); > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, > > + lower_32_bits(atu->pci_addr)); > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, > > + upper_32_bits(atu->pci_addr)); > > > > - val = type | PCIE_ATU_FUNC_NUM(func_no); > > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && > > dw_pcie_ver_is_ge(pci, 460A)) > > val |= PCIE_ATU_INCREASE_REGION_SIZE; > > if (dw_pcie_ver_is(pci, 490A)) > > val = dw_pcie_enable_ecrc(val); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val); > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); > > > > /* > > * Make sure ATU enable takes effect before any subsequent config > > * and I/O accesses. > > */ > > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { > > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2); > > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); > > if (val & PCIE_ATU_ENABLE) > > return 0; > > > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, > > return -ETIMEDOUT; > > } > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, > > - u64 cpu_addr, u64 pci_addr, u64 size) > > -{ > > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type, > > - cpu_addr, pci_addr, size); > > -} > > - > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, > > - int type, u64 cpu_addr, u64 pci_addr, > > - u64 size) > > -{ > > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type, > > - cpu_addr, pci_addr, size); > > -} > > - > > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) > > { > > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > index 755bcb406769..296c5b1ddc91 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -298,6 +298,15 @@ enum dw_pcie_ltssm { > > DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, > > }; > > > > +struct dw_pcie_ob_atu_cfg { > > + int index; > > + int type; > > + u8 func_no; > > + u64 cpu_addr; > > + u64 pci_addr; > > + u64 size; > > +}; > > + > > struct dw_pcie_host_ops { > > int (*host_init)(struct dw_pcie_rp *pp); > > void (*host_deinit)(struct dw_pcie_rp *pp); > > @@ -429,10 +438,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); > > int dw_pcie_link_up(struct dw_pcie *pci); > > void dw_pcie_upconfig_setup(struct dw_pcie *pci); > > int dw_pcie_wait_for_link(struct dw_pcie *pci); > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, > > - u64 cpu_addr, u64 pci_addr, u64 size); > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, > > - int type, u64 cpu_addr, u64 pci_addr, u64 size); > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > > + const struct dw_pcie_ob_atu_cfg *atu); > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, > > u64 cpu_addr, u64 pci_addr, u64 size); > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, > > -- > > 2.25.1 > >
Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support. To support them, modify PCIe DesignWare common codes. Changes from v19: https://lore.kernel.org/linux-pci/20230823091153.2578417-1-yoshihiro.shimoda.uh@renesas.com/ - Based on the latest pci.git / next branch and the following patches: [PATCH v3 0/2] Cleanup IRQ type definitions https://lore.kernel.org/linux-pci/20230802094036.1052472-1-dlemoal@kernel.org/ - Rename PCI_MSG_TYPE_R_* macros in the patch 01/19. - Fix the comment in the patch 04/19. - Add Reviewed-by in the patch {06,1[2678]/19. - Modify common functions for the same method of clock handling in the patch 1[78]/19. - Remove redundant gpio handling in the patch 16/19. Changes from v18: https://lore.kernel.org/linux-pci/20230721074452.65545-1-yoshihiro.shimoda.uh@renesas.com/ - Based on the latest pci.git / next branch and the following patches: [PATCH v3 0/2] Cleanup IRQ type definitions https://lore.kernel.org/linux-pci/20230802094036.1052472-1-dlemoal@kernel.org/ - Drop some patches about converting "legacy" to "INTx". - Add detailed description in the patch 0[26]/19. - Add a new patch "Expose dw_pcie_write_dbi2" in the patch 11/19. - Revise typo in the patch 12/19. - Fix calling order of deinit in the patch 12/19. - Revise Kconfig about kernel module names in the patch 1[67]/19. - Rename drivers' file names in the patch 1[67]/19. - Some other minor change/fix in the patch 1[67]/19. Yoshihiro Shimoda (19): PCI: Add INTx Mechanism Messages macros PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() PCI: dwc: Add outbound MSG TLPs support PCI: designware-ep: Add INTx IRQs support PCI: dwc: endpoint: Add multiple PFs support for dbi2 PCI: dwc: Add dw_pcie_link_set_max_link_width() PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting PCI: dwc: Add EDMA_UNROLL capability flag PCI: dwc: Expose dw_pcie_ep_exit() to module PCI: dwc: Expose dw_pcie_write_dbi2() to module PCI: dwc: endpoint: Introduce .pre_init() and .deinit() dt-bindings: PCI: dwc: Update maxItems of reg and reg-names dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller .../bindings/pci/rcar-gen4-pci-ep.yaml | 106 ++++++++ .../bindings/pci/rcar-gen4-pci-host.yaml | 123 ++++++++++ .../bindings/pci/snps,dw-pcie-ep.yaml | 4 +- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 4 +- MAINTAINERS | 1 + drivers/misc/pci_endpoint_test.c | 4 + drivers/pci/controller/dwc/Kconfig | 20 ++ drivers/pci/controller/dwc/Makefile | 4 + .../pci/controller/dwc/pcie-designware-ep.c | 136 +++++++++-- .../pci/controller/dwc/pcie-designware-host.c | 52 ++-- drivers/pci/controller/dwc/pcie-designware.c | 156 ++++++------ drivers/pci/controller/dwc/pcie-designware.h | 29 ++- .../controller/dwc/pcie-rcar-gen4-ep-drv.c | 173 +++++++++++++ .../controller/dwc/pcie-rcar-gen4-host-drv.c | 135 +++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.c | 227 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - drivers/pci/pci.h | 18 ++ 18 files changed, 1111 insertions(+), 131 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep-drv.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host-drv.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h