| Message ID | 20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org |
|---|---|
| Headers | show |
| Series | drm/msm: Add SM6125 MDSS/DPU hardware and enable Sony Xperia 10 II panel | expand |
On 27.06.2023 22:14, Marijn Suijten wrote: > The regulator setup was likely copied from other SoCs by mistake. Just > like SM6125 the DSI PHY on this platform is not getting power from a > regulator but from the MX power domain. > > Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 3ce45b023e63..31deda1c664a 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -1087,8 +1087,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { > > const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { > .has_phy_lane = true, > - .regulator_data = dsi_phy_14nm_17mA_regulators, > - .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), > .ops = { > .enable = dsi_14nm_phy_enable, > .disable = dsi_14nm_phy_disable, >
On 27.06.2023 22:14, Marijn Suijten wrote: > SM6125 features only a single PHY (despite a secondary PHY PLL source > being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream > sources for this "trinket" SoC do not define the typical "vcca" > regulator to be available nor used. This, including the register offset > is identical to QCM2290, whose config struct can trivially be reused. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 9d5795c58a98..05621e5e7d63 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_14nm_660_cfgs }, > { .compatible = "qcom,dsi-phy-14nm-8953", > .data = &dsi_phy_14nm_8953_cfgs }, > + { .compatible = "qcom,sm6125-dsi-phy-14nm", > + .data = &dsi_phy_14nm_2290_cfgs }, > #endif > #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY > { .compatible = "qcom,dsi-phy-10nm", >
On 27.06.2023 22:14, Marijn Suijten wrote: > Add the DT nodes that describe the MDSS hardware on SM6125, containing > one MDP (display controller) together with a single DSI and DSI PHY. No > DisplayPort support is added for now. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm6125.dtsi | 191 ++++++++++++++++++++++++++++++++++- > 1 file changed, 189 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index a5cc0d43d2d9..b21fa1256f95 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -1204,12 +1204,199 @@ sram@4690000 { > reg = <0x04690000 0x10000>; > }; > > + mdss: display-subsystem@5e00000 { > + compatible = "qcom,sm6125-mdss"; > + reg = <0x05e00000 0x1000>; > + reg-names = "mdss"; > + > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + > + iommus = <&apps_smmu 0x400 0x0>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + status = "disabled"; > + > + mdss_mdp: display-controller@5e01000 { > + compatible = "qcom,sm6125-dpu"; > + reg = <0x05e01000 0x83208>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "iface", > + "rot", > + "lut", > + "core", > + "vsync"; > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6125_VDDCX>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-192000000 { > + opp-hz = /bits/ 64 <192000000>; > + required-opps = <&rpmpd_opp_low_svs>; > + }; > + > + opp-256000000 { > + opp-hz = /bits/ 64 <256000000>; > + required-opps = <&rpmpd_opp_svs>; > + }; > + > + opp-307200000 { > + opp-hz = /bits/ 64 <307200000>; > + required-opps = <&rpmpd_opp_svs_plus>; > + }; > + > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + required-opps = <&rpmpd_opp_nom>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + required-opps = <&rpmpd_opp_turbo>; > + }; > + }; > + }; > + > + mdss_dsi0: dsi@5e94000 { > + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > + reg = <0x05e94000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmpd SM6125_VDDCX>; > + > + phys = <&mdss_dsi0_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dsi0_out: endpoint { > + }; > + }; > + }; > + > + dsi_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-164000000 { > + opp-hz = /bits/ 64 <164000000>; > + required-opps = <&rpmpd_opp_low_svs>; > + }; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmpd_opp_svs>; > + }; > + }; > + }; > + > + mdss_dsi0_phy: phy@5e94400 { > + compatible = "qcom,sm6125-dsi-phy-14nm"; > + reg = <0x05e94400 0x100>, > + <0x05e94500 0x300>, > + <0x05e94800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "iface", > + "ref"; > + > + required-opps = <&rpmpd_opp_svs>; > + power-domains = <&rpmpd SM6125_VDDMX>; > + > + status = "disabled"; > + }; > + }; > + > dispcc: clock-controller@5f00000 { > compatible = "qcom,sm6125-dispcc"; > reg = <0x05f00000 0x20000>; > clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > - <0>, > - <0>, > + <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>, > <0>, > <0>, > <0>, >
On 27.06.2023 22:14, Marijn Suijten wrote: > Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01 > 6.0" 1080x2520 panel. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 ++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts > index 9f8a9ef398a2..08d96d05da2e 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts > +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts > @@ -179,6 +179,43 @@ &i2c3 { > /* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */ > }; > > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dsi0 { > + vdda-supply = <&pm6125_l18>; > + status = "okay"; > + > + panel@0 { > + compatible = "samsung,sofef01-m-ams597ut01"; > + reg = <0>; > + > + reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>; > + > + vddio-supply = <&pm6125_l12>; > + > + pinctrl-0 = <&mdss_dsi_active &mdss_te_active_sleep>; > + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_active_sleep>; > + pinctrl-names = "default", "sleep"; > + > + port { > + panel_in: endpoint { > + remote-endpoint = <&mdss_dsi0_out>; > + }; > + }; > + }; > +}; > + > +&mdss_dsi0_out { > + remote-endpoint = <&panel_in>; > + data-lanes = <0 1 2 3>; > +}; > + > +&mdss_dsi0_phy { > + status = "okay"; > +}; > + > &pm6125_adc { > pinctrl-names = "default"; > pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; > @@ -469,6 +506,28 @@ vol_down_n: vol-down-n-state { > drive-strength = <2>; > bias-disable; > }; > + > + mdss_te_active_sleep: mdss-te-active-sleep-state { > + pins = "gpio89"; > + function = "mdp_vsync"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + mdss_dsi_active: mdss-dsi-active-state { > + pins = "gpio90"; > + function = "gpio"; > + drive-strength = <8>; > + bias-disable; > + }; > + > + mdss_dsi_sleep: mdss-dsi-sleep-state { > + pins = "gpio90"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > }; > > &usb3 { >
On 27/06/2023 23:14, Marijn Suijten wrote: > The regulator setup was likely copied from other SoCs by mistake. Just > like SM6125 the DSI PHY on this platform is not getting power from a > regulator but from the MX power domain. > > Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -- > 1 file changed, 2 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 27/06/2023 23:14, Marijn Suijten wrote: > Add definitions for the display hardware used on the Qualcomm SM6125 > platform. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 230 +++++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 4 files changed, 238 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 27/06/2023 23:14, Marijn Suijten wrote: > SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++ > 1 file changed, 8 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 27/06/2023 23:14, Marijn Suijten wrote: > SM6125 features only a single PHY (despite a secondary PHY PLL source > being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream > sources for this "trinket" SoC do not define the typical "vcca" > regulator to be available nor used. This, including the register offset > is identical to QCM2290, whose config struct can trivially be reused. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 27/06/2023 23:14, Marijn Suijten wrote: > We have a working RPM XO clock; no other driver except rpmcc should be > parenting directly to the fixed-factor xo_board clock nor should it be > reachable by that global name. Remove the name to that effect, so that > every clock relation is explicitly defined in DTS. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index 722dde560bec..edb03508dba3 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -22,7 +22,6 @@ xo_board: xo-board { > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <19200000>; > - clock-output-names = "xo_board"; Why? I'd say, leave it. With that fixed: Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > }; > > sleep_clk: sleep-clk { > @@ -306,6 +305,8 @@ rpm_requests: rpm-requests { > rpmcc: clock-controller { > compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; > #clock-cells = <1>; > + clocks = <&xo_board>; > + clock-names = "xo"; > }; > > rpmpd: power-controller { > @@ -713,7 +714,7 @@ sdhc_1: mmc@4744000 { > > clocks = <&gcc GCC_SDCC1_AHB_CLK>, > <&gcc GCC_SDCC1_APPS_CLK>, > - <&xo_board>; > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "core", "xo"; > iommus = <&apps_smmu 0x160 0x0>; > > @@ -740,7 +741,7 @@ sdhc_2: mmc@4784000 { > > clocks = <&gcc GCC_SDCC2_AHB_CLK>, > <&gcc GCC_SDCC2_APPS_CLK>, > - <&xo_board>; > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > clock-names = "iface", "core", "xo"; > iommus = <&apps_smmu 0x180 0x0>; > >
On 27/06/2023 23:14, Marijn Suijten wrote: > Enable and configure the dispcc node on SM6125 for consumption by MDSS > later on. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index edb03508dba3..a5cc0d43d2d9 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > */ > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > @@ -1203,6 +1204,30 @@ sram@4690000 { > reg = <0x04690000 0x10000>; > }; > > + dispcc: clock-controller@5f00000 { > + compatible = "qcom,sm6125-dispcc"; > + reg = <0x05f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk", > + "cfg_ahb_clk", > + "gcc_disp_gpll0_div_clk_src"; > + power-domains = <&rpmpd SM6125_VDDCX>; Would it be logical to specify the required-opps too? > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > apps_smmu: iommu@c600000 { > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0c600000 0x80000>; >
On 27/06/2023 23:14, Marijn Suijten wrote: > Add the DT nodes that describe the MDSS hardware on SM6125, containing > one MDP (display controller) together with a single DSI and DSI PHY. No > DisplayPort support is added for now. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 191 ++++++++++++++++++++++++++++++++++- > 1 file changed, 189 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index a5cc0d43d2d9..b21fa1256f95 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -1204,12 +1204,199 @@ sram@4690000 { > reg = <0x04690000 0x10000>; > }; > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 2023-06-29 13:55:28, Dmitry Baryshkov wrote: > On 27/06/2023 23:14, Marijn Suijten wrote: > > We have a working RPM XO clock; no other driver except rpmcc should be > > parenting directly to the fixed-factor xo_board clock nor should it be > > reachable by that global name. Remove the name to that effect, so that > > every clock relation is explicitly defined in DTS. > > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > --- > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++--- > > 1 file changed, 4 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > index 722dde560bec..edb03508dba3 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > @@ -22,7 +22,6 @@ xo_board: xo-board { > > compatible = "fixed-clock"; > > #clock-cells = <0>; > > clock-frequency = <19200000>; > > - clock-output-names = "xo_board"; > > Why? I'd say, leave it. The exact reason is explained in the commit message. > > With that fixed: Hence I don't think it makes sense to "fix" this. - Marijn > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: > On 27/06/2023 23:14, Marijn Suijten wrote: > > Enable and configure the dispcc node on SM6125 for consumption by MDSS > > later on. > > > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > --- > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > index edb03508dba3..a5cc0d43d2d9 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > @@ -3,6 +3,7 @@ > > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > > */ > > > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > > #include <dt-bindings/clock/qcom,rpmcc.h> > > #include <dt-bindings/dma/qcom-gpi.h> > > @@ -1203,6 +1204,30 @@ sram@4690000 { > > reg = <0x04690000 0x10000>; > > }; > > > > + dispcc: clock-controller@5f00000 { > > + compatible = "qcom,sm6125-dispcc"; > > + reg = <0x05f00000 0x20000>; > > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > > + <0>, > > + <0>, > > + <0>, > > + <0>, > > + <0>, > > + <&gcc GCC_DISP_AHB_CLK>, > > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > > + clock-names = "bi_tcxo", > > + "dsi0_phy_pll_out_byteclk", > > + "dsi0_phy_pll_out_dsiclk", > > + "dsi1_phy_pll_out_dsiclk", > > + "dp_phy_pll_link_clk", > > + "dp_phy_pll_vco_div_clk", > > + "cfg_ahb_clk", > > + "gcc_disp_gpll0_div_clk_src"; > > + power-domains = <&rpmpd SM6125_VDDCX>; > > Would it be logical to specify the required-opps too? Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI PHY despite not having a reference value downstream (it sets a range of NOM-TURBO_NO_CPR, and RETENTION when it's off). - Marijn > > > + #clock-cells = <1>; > > + #power-domain-cells = <1>; > > + }; > > + > > apps_smmu: iommu@c600000 { > > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > > reg = <0x0c600000 0x80000>; > > > > -- > With best wishes > Dmitry >
On Thu, 29 Jun 2023 at 15:14, Marijn Suijten <marijn.suijten@somainline.org> wrote: > > On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: > > On 27/06/2023 23:14, Marijn Suijten wrote: > > > Enable and configure the dispcc node on SM6125 for consumption by MDSS > > > later on. > > > > > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > > --- > > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ > > > 1 file changed, 25 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > index edb03508dba3..a5cc0d43d2d9 100644 > > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > @@ -3,6 +3,7 @@ > > > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > > > */ > > > > > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > > > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > > > #include <dt-bindings/clock/qcom,rpmcc.h> > > > #include <dt-bindings/dma/qcom-gpi.h> > > > @@ -1203,6 +1204,30 @@ sram@4690000 { > > > reg = <0x04690000 0x10000>; > > > }; > > > > > > + dispcc: clock-controller@5f00000 { > > > + compatible = "qcom,sm6125-dispcc"; > > > + reg = <0x05f00000 0x20000>; > > > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > > > + <0>, > > > + <0>, > > > + <0>, > > > + <0>, > > > + <0>, > > > + <&gcc GCC_DISP_AHB_CLK>, > > > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > > > + clock-names = "bi_tcxo", > > > + "dsi0_phy_pll_out_byteclk", > > > + "dsi0_phy_pll_out_dsiclk", > > > + "dsi1_phy_pll_out_dsiclk", > > > + "dp_phy_pll_link_clk", > > > + "dp_phy_pll_vco_div_clk", > > > + "cfg_ahb_clk", > > > + "gcc_disp_gpll0_div_clk_src"; > > > + power-domains = <&rpmpd SM6125_VDDCX>; > > > > Would it be logical to specify the required-opps too? > > Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. > What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI > PHY despite not having a reference value downstream (it sets a range of > NOM-TURBO_NO_CPR, and RETENTION when it's off). Then for DSI PHY the required-opps should be rpmpd_opp_nom. For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, should be enough. > > - Marijn > > > > > > + #clock-cells = <1>; > > > + #power-domain-cells = <1>; > > > + }; > > > + > > > apps_smmu: iommu@c600000 { > > > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > > > reg = <0x0c600000 0x80000>; > > > > > > > -- > > With best wishes > > Dmitry > >
On Thu, 29 Jun 2023 at 15:09, Marijn Suijten <marijn.suijten@somainline.org> wrote: > > On 2023-06-29 13:55:28, Dmitry Baryshkov wrote: > > On 27/06/2023 23:14, Marijn Suijten wrote: > > > We have a working RPM XO clock; no other driver except rpmcc should be > > > parenting directly to the fixed-factor xo_board clock nor should it be > > > reachable by that global name. Remove the name to that effect, so that > > > every clock relation is explicitly defined in DTS. > > > > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > > --- > > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++--- > > > 1 file changed, 4 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > index 722dde560bec..edb03508dba3 100644 > > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > > > @@ -22,7 +22,6 @@ xo_board: xo-board { > > > compatible = "fixed-clock"; > > > #clock-cells = <0>; > > > clock-frequency = <19200000>; > > > - clock-output-names = "xo_board"; > > > > Why? I'd say, leave it. > > The exact reason is explained in the commit message. Usually we do no not kill the xo_board name for the sake of anybody still looking for the old name. Weak argument, I know. > > > > > With that fixed: > > Hence I don't think it makes sense to "fix" this. > > - Marijn > > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 29.06.2023 14:26, Dmitry Baryshkov wrote: > On Thu, 29 Jun 2023 at 15:09, Marijn Suijten > <marijn.suijten@somainline.org> wrote: >> >> On 2023-06-29 13:55:28, Dmitry Baryshkov wrote: >>> On 27/06/2023 23:14, Marijn Suijten wrote: >>>> We have a working RPM XO clock; no other driver except rpmcc should be >>>> parenting directly to the fixed-factor xo_board clock nor should it be >>>> reachable by that global name. Remove the name to that effect, so that >>>> every clock relation is explicitly defined in DTS. >>>> >>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++--- >>>> 1 file changed, 4 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> index 722dde560bec..edb03508dba3 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> @@ -22,7 +22,6 @@ xo_board: xo-board { >>>> compatible = "fixed-clock"; >>>> #clock-cells = <0>; >>>> clock-frequency = <19200000>; >>>> - clock-output-names = "xo_board"; >>> >>> Why? I'd say, leave it. >> >> The exact reason is explained in the commit message. > > Usually we do no not kill the xo_board name for the sake of anybody > still looking for the old name. Weak argument, I know. The only users are (rg -l '"xo_board"' drivers): drivers/clk/qcom/mmcc-msm8974.c drivers/clk/qcom/a53-pll.c drivers/clk/qcom/gcc-msm8974.c drivers/clk/qcom/clk-smd-rpm.c drivers/clk/qcom/mmcc-msm8996.c drivers/clk/qcom/gcc-msm8916.c drivers/clk/qcom/gcc-apq8084.c drivers/clk/qcom/gcc-msm8996.c drivers/clk/qcom/mmcc-apq8084.c drivers/clk/qcom/clk-rpmh.c drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c This platform only binds clk-smd-rpm, but patch 11 provides a direct reference in the DT. Konrad > >> >>> >>> With that fixed: >> >> Hence I don't think it makes sense to "fix" this. >> >> - Marijn >> >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > >
On 29.06.2023 14:24, Dmitry Baryshkov wrote: > On Thu, 29 Jun 2023 at 15:14, Marijn Suijten > <marijn.suijten@somainline.org> wrote: >> >> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: >>> On 27/06/2023 23:14, Marijn Suijten wrote: >>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS >>>> later on. >>>> >>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ >>>> 1 file changed, 25 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> index edb03508dba3..a5cc0d43d2d9 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> @@ -3,6 +3,7 @@ >>>> * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> >>>> */ >>>> >>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> >>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h> >>>> #include <dt-bindings/clock/qcom,rpmcc.h> >>>> #include <dt-bindings/dma/qcom-gpi.h> >>>> @@ -1203,6 +1204,30 @@ sram@4690000 { >>>> reg = <0x04690000 0x10000>; >>>> }; >>>> >>>> + dispcc: clock-controller@5f00000 { >>>> + compatible = "qcom,sm6125-dispcc"; >>>> + reg = <0x05f00000 0x20000>; >>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <&gcc GCC_DISP_AHB_CLK>, >>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; >>>> + clock-names = "bi_tcxo", >>>> + "dsi0_phy_pll_out_byteclk", >>>> + "dsi0_phy_pll_out_dsiclk", >>>> + "dsi1_phy_pll_out_dsiclk", >>>> + "dp_phy_pll_link_clk", >>>> + "dp_phy_pll_vco_div_clk", >>>> + "cfg_ahb_clk", >>>> + "gcc_disp_gpll0_div_clk_src"; >>>> + power-domains = <&rpmpd SM6125_VDDCX>; >>> >>> Would it be logical to specify the required-opps too? >> >> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. >> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI >> PHY despite not having a reference value downstream (it sets a range of >> NOM-TURBO_NO_CPR, and RETENTION when it's off). > > Then for DSI PHY the required-opps should be rpmpd_opp_nom. Yes > > For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, > should be enough. I'm not 100% sure but not specifying an opp and turning on the domain *******probably******* just sticks with the lowest vote Konrad > >> >> - Marijn >> >>> >>>> + #clock-cells = <1>; >>>> + #power-domain-cells = <1>; >>>> + }; >>>> + >>>> apps_smmu: iommu@c600000 { >>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>>> reg = <0x0c600000 0x80000>; >>>> >>> >>> -- >>> With best wishes >>> Dmitry >>> > > >
On 29/06/2023 22:53, Konrad Dybcio wrote: > On 29.06.2023 14:24, Dmitry Baryshkov wrote: >> On Thu, 29 Jun 2023 at 15:14, Marijn Suijten >> <marijn.suijten@somainline.org> wrote: >>> >>> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: >>>> On 27/06/2023 23:14, Marijn Suijten wrote: >>>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS >>>>> later on. >>>>> >>>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ >>>>> 1 file changed, 25 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> index edb03508dba3..a5cc0d43d2d9 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> @@ -3,6 +3,7 @@ >>>>> * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> >>>>> */ >>>>> >>>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> >>>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h> >>>>> #include <dt-bindings/clock/qcom,rpmcc.h> >>>>> #include <dt-bindings/dma/qcom-gpi.h> >>>>> @@ -1203,6 +1204,30 @@ sram@4690000 { >>>>> reg = <0x04690000 0x10000>; >>>>> }; >>>>> >>>>> + dispcc: clock-controller@5f00000 { >>>>> + compatible = "qcom,sm6125-dispcc"; >>>>> + reg = <0x05f00000 0x20000>; >>>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>>> + <0>, >>>>> + <0>, >>>>> + <0>, >>>>> + <0>, >>>>> + <0>, >>>>> + <&gcc GCC_DISP_AHB_CLK>, >>>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; >>>>> + clock-names = "bi_tcxo", >>>>> + "dsi0_phy_pll_out_byteclk", >>>>> + "dsi0_phy_pll_out_dsiclk", >>>>> + "dsi1_phy_pll_out_dsiclk", >>>>> + "dp_phy_pll_link_clk", >>>>> + "dp_phy_pll_vco_div_clk", >>>>> + "cfg_ahb_clk", >>>>> + "gcc_disp_gpll0_div_clk_src"; >>>>> + power-domains = <&rpmpd SM6125_VDDCX>; >>>> >>>> Would it be logical to specify the required-opps too? >>> >>> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. >>> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI >>> PHY despite not having a reference value downstream (it sets a range of >>> NOM-TURBO_NO_CPR, and RETENTION when it's off). >> >> Then for DSI PHY the required-opps should be rpmpd_opp_nom. > Yes > >> >> For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, >> should be enough. > I'm not 100% sure but not specifying an opp and turning on the domain > *******probably******* just sticks with the lowest vote I think so too. But I think it might be better to be explicit rather than being implicit here. Both of us are describing Linux behaviour (=set lowest possible value), while DT should describe the hardware. > > Konrad >> >>> >>> - Marijn >>> >>>> >>>>> + #clock-cells = <1>; >>>>> + #power-domain-cells = <1>; >>>>> + }; >>>>> + >>>>> apps_smmu: iommu@c600000 { >>>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>>>> reg = <0x0c600000 0x80000>; >>>>> >>>> >>>> -- >>>> With best wishes >>>> Dmitry >>>> >> >> >>
On Tue, 27 Jun 2023 22:14:15 +0200, Marijn Suijten wrote: > Bring up the SM6125 DPU now that all preliminary series (such as INTF > TE) have been merged (for me to test the hardware properly), and most > other conflicting work (barring ongoing catalog *improvements*) has made > its way in as well or is still being discussed. > > The second part of the series complements that by immediately utilizing > this hardware in DT, and even enabling the MDSS/DSI nodes complete with > a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II). > > [...] Applied, thanks! [05/15] dt-bindings: display/msm: dsi-controller-main: Document SM6125 https://gitlab.freedesktop.org/lumag/msm/-/commit/4d125651038a [06/15] dt-bindings: display/msm: sc7180-dpu: Describe SM6125 https://gitlab.freedesktop.org/lumag/msm/-/commit/6321c42645b2 [07/15] dt-bindings: display/msm: Add SM6125 MDSS https://gitlab.freedesktop.org/lumag/msm/-/commit/a628b5b16872 [08/15] drm/msm/dpu: Add SM6125 support https://gitlab.freedesktop.org/lumag/msm/-/commit/01077e7c890f [09/15] drm/msm/mdss: Add SM6125 support https://gitlab.freedesktop.org/lumag/msm/-/commit/c6da55b771de [10/15] dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant https://gitlab.freedesktop.org/lumag/msm/-/commit/d44ddd646858 [11/15] drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125 https://gitlab.freedesktop.org/lumag/msm/-/commit/ac2f330f92f2 Best regards,
On 6/27/2023 1:14 PM, Marijn Suijten wrote: > The regulator setup was likely copied from other SoCs by mistake. Just > like SM6125 the DSI PHY on this platform is not getting power from a > regulator but from the MX power domain. > > Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -- > 1 file changed, 2 deletions(-) > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
On Tue, 27 Jun 2023 22:14:15 +0200, Marijn Suijten wrote: > Bring up the SM6125 DPU now that all preliminary series (such as INTF > TE) have been merged (for me to test the hardware properly), and most > other conflicting work (barring ongoing catalog *improvements*) has made > its way in as well or is still being discussed. > > The second part of the series complements that by immediately utilizing > this hardware in DT, and even enabling the MDSS/DSI nodes complete with > a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II). > > [...] Applied, thanks! [01/15] drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config https://gitlab.freedesktop.org/drm/msm/-/commit/97368254a08e Best regards,
On 2023-06-29 21:14:47, Konrad Dybcio wrote: > On 29.06.2023 14:26, Dmitry Baryshkov wrote: > > On Thu, 29 Jun 2023 at 15:09, Marijn Suijten > > <marijn.suijten@somainline.org> wrote: > >> > >> On 2023-06-29 13:55:28, Dmitry Baryshkov wrote: > >>> On 27/06/2023 23:14, Marijn Suijten wrote: > >>>> We have a working RPM XO clock; no other driver except rpmcc should be > >>>> parenting directly to the fixed-factor xo_board clock nor should it be > >>>> reachable by that global name. Remove the name to that effect, so that > >>>> every clock relation is explicitly defined in DTS. > >>>> > >>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > >>>> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > >>>> --- > >>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++--- > >>>> 1 file changed, 4 insertions(+), 3 deletions(-) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > >>>> index 722dde560bec..edb03508dba3 100644 > >>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > >>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > >>>> @@ -22,7 +22,6 @@ xo_board: xo-board { > >>>> compatible = "fixed-clock"; > >>>> #clock-cells = <0>; > >>>> clock-frequency = <19200000>; > >>>> - clock-output-names = "xo_board"; > >>> > >>> Why? I'd say, leave it. > >> > >> The exact reason is explained in the commit message. > > > > Usually we do no not kill the xo_board name for the sake of anybody > > still looking for the old name. Weak argument, I know. > The only users are (rg -l '"xo_board"' drivers): > > drivers/clk/qcom/mmcc-msm8974.c > drivers/clk/qcom/a53-pll.c > drivers/clk/qcom/gcc-msm8974.c > drivers/clk/qcom/clk-smd-rpm.c > drivers/clk/qcom/mmcc-msm8996.c > drivers/clk/qcom/gcc-msm8916.c > drivers/clk/qcom/gcc-apq8084.c > drivers/clk/qcom/gcc-msm8996.c > drivers/clk/qcom/mmcc-apq8084.c > drivers/clk/qcom/clk-rpmh.c > drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c > > This platform only binds clk-smd-rpm, but patch 11 provides a > direct reference in the DT. And following a quick check, those occurrences all have .fw_name="xo",.name="xo_board", allowing the clock to be provided via DT. For sm6125, I'd like it to be required like that: all dt-bindings require an "xo" board where relevant, after all. - Marijn > > Konrad > > > > >> > >>> > >>> With that fixed: > >> > >> Hence I don't think it makes sense to "fix" this. > >> > >> - Marijn > >> > >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > > > >
Bring up the SM6125 DPU now that all preliminary series (such as INTF TE) have been merged (for me to test the hardware properly), and most other conflicting work (barring ongoing catalog *improvements*) has made its way in as well or is still being discussed. The second part of the series complements that by immediately utilizing this hardware in DT, and even enabling the MDSS/DSI nodes complete with a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II). The last patch ("sm6125-seine: Configure MDSS, DSI and panel") depends on (an impending v2 of) my Sony panel collection series [1]. [1]: https://lore.kernel.org/linux-arm-msm/20230521-drm-panels-sony-v1-0-541c341d6bee@somainline.org/ --- Changes in v2: - Moved dispcc DT clock reordering to the right patch (--fixup on the wrong hash) (Dmitry, Konrad multiple times); - Drop removal of GCC_DISP_AHB_CLK in dispcc bindings. While it is unused in the current driver, it is likely used to ensure a guaranteed probe order between GCC and DISPCC downstream, as well as currently relying on the fact that GCC_DISP_AHB_CLK is CLK_IS_CRITICAL and never turned off (Bjorn); - Add GCC_DISP_GPLL0_DIV_CLK_SRC at the end of the dispcc clock list to maintain some form of ABI stability (Krzysztof); - Use SoC-prefix format for 14nm DSI PHY qcom,sm6125-dsi-phy-14nm compatible (Dmitry, Krzysztof); - Add patch to drop unused regulators from QCM2290 14nm DSI PHY (Konrad, Dmitry); - Reuse QCM2290 14nm DSI PHY config struct for SM6125 compatible (Konrad); - s/sde/mdss in pdx201.dts pinctrl node names and labels (Konrad); - Use MX power domain in DSI PHY with SVS OPP (Dmitry); - Use CX power domain with (already-existing) OPP table in DSI CTRL (Konrad, Dmitry); - Rebased on top of DPU catalog rework [1] by inlining macro invocations, and validated by diffing stripped dpu_hw_catalog.o that there are no unexpected changes; - Unset min_llcc_ib because this platform has no LLCC (Konrad); - Fix UBWC comment to mention "encoding" version (Dmitry); - Reordered DT nodes to follow Konrad's requested sorting; - Add power-domains and required-opps properties to dsi-phy-14nm.yaml; - Link to v1: https://lore.kernel.org/r/20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org The discussions and this list ran quite long, apologies if I missed or mis-resolved anything in advance! [1]: https://lore.kernel.org/linux-arm-msm/20230619212519.875673-1-dmitry.baryshkov@linaro.org/ --- Marijn Suijten (15): drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg dt-bindings: clock: qcom,dispcc-sm6125: Require GCC PLL0 DIV clock dt-bindings: clock: qcom,dispcc-sm6125: Allow power-domains property dt-bindings: display/msm: dsi-controller-main: Document SM6125 dt-bindings: display/msm: sc7180-dpu: Describe SM6125 dt-bindings: display/msm: Add SM6125 MDSS drm/msm/dpu: Add SM6125 support drm/msm/mdss: Add SM6125 support dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125 arm64: dts: qcom: sm6125: Switch fixed xo_board clock to RPM XO clock arm64: dts: qcom: sm6125: Add dispcc node arm64: dts: qcom: sm6125: Add display hardware nodes arm64: dts: qcom: sm6125-seine: Configure MDSS, DSI and panel .../bindings/clock/qcom,dispcc-sm6125.yaml | 15 +- .../bindings/display/msm/dsi-controller-main.yaml | 2 + .../bindings/display/msm/dsi-phy-14nm.yaml | 11 + .../bindings/display/msm/qcom,sc7180-dpu.yaml | 14 ++ .../bindings/display/msm/qcom,sm6125-mdss.yaml | 217 ++++++++++++++++++ .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 +++++ arch/arm64/boot/dts/qcom/sm6125.dtsi | 251 +++++++++++++++++++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 230 +++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 - drivers/gpu/drm/msm/msm_mdss.c | 8 + 14 files changed, 796 insertions(+), 23 deletions(-) --- base-commit: e42c42a03fdf31deccaea2f44885dd6f8150eb32 change-id: 20230624-sm6125-dpu-aedc9637ee7b Best regards,