[00/18] arm64: qcom: add support for sa8775p-ride

From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

This adds basic support for the Qualcomm sa8775p platform and its reference
board: sa8775p-ride. The dtsi contains basic SoC description required for
a simple boot-to-shell. The dts enables boot-to-shell with UART on the
sa8775p-ride board. There are three new drivers required to boot the board:
pinctrl, interconnect and GCC clock. Other patches contain various tweaks
to existing code. More support is coming up.

Bartosz Golaszewski (15):
  dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p
  arm64: defconfig: enable the clock driver for Qualcomm SA8775P
    platforms
  dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p
  clk: qcom: rpmh: add clocks for sa8775p
  dt-bindings: interconnect: qcom: document the interconnects for
    sa8775p
  arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P
  dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm
  arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P
    platforms
  dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
  dt-bindings: power: qcom,rpmpd: document sa8775p
  soc: qcom: rmphpd: add power domains for sa8775p
  dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P
  iommu: arm-smmu: qcom: add support for sa8775p
  dt-bindings: arm: qcom: document the sa8775p reference board
  arm64: dts: qcom: add initial support for qcom sa8775p-ride

Shazad Hussain (2):
  clk: qcom: add the GCC driver for sa8775p
  interconnect: qcom: add a driver for sa8775p

Yadu MG (1):
  pinctrl: qcom: sa8775p: add the pinctrl driver for the sa8775p
    platform

 .../devicetree/bindings/arm/qcom.yaml         |    5 +
 .../bindings/clock/qcom,gcc-sa8775p.yaml      |   77 +
 .../bindings/clock/qcom,rpmhcc.yaml           |    1 +
 .../bindings/interconnect/qcom,rpmh.yaml      |   14 +
 .../devicetree/bindings/iommu/arm,smmu.yaml   |    1 +
 .../bindings/mailbox/qcom-ipcc.yaml           |    1 +
 .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml   |  142 +
 .../devicetree/bindings/power/qcom,rpmpd.yaml |    1 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts     |   39 +
 arch/arm64/boot/dts/qcom/sa8775p.dtsi         |  841 +++
 arch/arm64/configs/defconfig                  |    3 +
 drivers/clk/qcom/Kconfig                      |    9 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-rpmh.c                   |   17 +
 drivers/clk/qcom/gcc-sa8775p.c                | 4806 +++++++++++++++++
 drivers/interconnect/qcom/Kconfig             |    9 +
 drivers/interconnect/qcom/Makefile            |    2 +
 drivers/interconnect/qcom/sa8775p.c           | 2542 +++++++++
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c    |    1 +
 drivers/pinctrl/qcom/Kconfig                  |    9 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-sa8775p.c        | 1649 ++++++
 drivers/soc/qcom/rpmhpd.c                     |   34 +
 include/dt-bindings/clock/qcom,gcc-sa8775p.h  |  320 ++
 .../dt-bindings/interconnect/qcom,sa8775p.h   |  231 +
 include/dt-bindings/power/qcom-rpmpd.h        |   19 +
 27 files changed, 10776 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
 create mode 100644 drivers/clk/qcom/gcc-sa8775p.c
 create mode 100644 drivers/interconnect/qcom/sa8775p.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sa8775p.h
 create mode 100644 include/dt-bindings/interconnect/qcom,sa8775p.h

On 9.01.2023 18:44, Bartosz Golaszewski wrote:
> From: Shazad Hussain <quic_shazhuss@quicinc.com>
> 
> Add support for the Global Clock Controller found in the QTI SA8775P
> platforms.
> 
> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> [Bartosz: made the driver ready for upstream]
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
[...]

> +
> +static struct gdsc usb20_prim_gdsc = {
> +	.gdscr = 0x1C004,
Please use lowercase hex literals outside #defines.

> +	.pd = {
> +		.name = "usb20_prim_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +};
> +
[...]

> +
> +static const struct regmap_config gcc_sa8775p_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x472cffc,
This is faaaaar more than what your DT node specifies.

With these two fixed, LGTM:

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
> +	.fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_sa8775p_desc = {
> +	.config = &gcc_sa8775p_regmap_config,
> +	.clks = gcc_sa8775p_clocks,
> +	.num_clks = ARRAY_SIZE(gcc_sa8775p_clocks),
> +	.resets = gcc_sa8775p_resets,
> +	.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
> +	.gdscs = gcc_sa8775p_gdscs,
> +	.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
> +};
> +
> +static const struct of_device_id gcc_sa8775p_match_table[] = {
> +	{ .compatible = "qcom,gcc-sa8775p" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table);
> +
> +static int gcc_sa8775p_probe(struct platform_device *pdev)
> +{
> +	struct regmap *regmap;
> +	int ret;
> +
> +	regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> +				       ARRAY_SIZE(gcc_dfs_clocks));
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Keep the clocks always-ON
> +	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK,
> +	 * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
> +	 * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK.
> +	 */
> +	regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0));
> +	regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0));
> +
> +	return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
> +}
> +
> +static struct platform_driver gcc_sa8775p_driver = {
> +	.probe = gcc_sa8775p_probe,
> +	.driver = {
> +		.name = "gcc-sa8775p",
> +		.of_match_table = gcc_sa8775p_match_table,
> +	},
> +};
> +
> +static int __init gcc_sa8775p_init(void)
> +{
> +	return platform_driver_register(&gcc_sa8775p_driver);
> +}
> +subsys_initcall(gcc_sa8775p_init);
> +
> +static void __exit gcc_sa8775p_exit(void)
> +{
> +	platform_driver_unregister(&gcc_sa8775p_driver);
> +}
> +module_exit(gcc_sa8775p_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver");
> +MODULE_LICENSE("GPL");

On 9.01.2023 18:44, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Enable the GCC clock driver on SA8775P platforms. It needs to be built-in
> for console to work.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 851e8f9be06d..1cb586125c46 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1098,6 +1098,7 @@ CONFIG_MSM_GCC_8994=y
>  CONFIG_MSM_MMCC_8996=y
>  CONFIG_MSM_GCC_8998=y
>  CONFIG_QCS_GCC_404=y
> +CONFIG_SA_GCC_8775P=y
>  CONFIG_SC_GCC_7180=y
>  CONFIG_SC_GCC_7280=y
>  CONFIG_SC_GCC_8180X=y

On 9.01.2023 18:44, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Hm.. are you sending this from the correct email? Not that it
matters *that* much, authorship is more important..

> 
> Extend the driver with a description of clocks for sa8775p platforms.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/clk/qcom/clk-rpmh.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 586a810c682c..d5f7ec2edbbe 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -396,6 +396,22 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
>  	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
>  };
>  
> +static struct clk_hw *sa8775p_rpmh_clocks[] = {
> +	[RPMH_CXO_CLK]		= &clk_rpmh_bi_tcxo_div2.hw,
> +	[RPMH_CXO_CLK_A]	= &clk_rpmh_bi_tcxo_div2_ao.hw,
> +	[RPMH_LN_BB_CLK1]	= &clk_rpmh_ln_bb_clk1_a2.hw,
> +	[RPMH_LN_BB_CLK2]	= &clk_rpmh_ln_bb_clk2_a2.hw,
> +	[RPMH_LN_BB_CLK2_A]	= &clk_rpmh_ln_bb_clk2_a4_ao.hw,
> +	[RPMH_IPA_CLK]		= &clk_rpmh_ipa.hw,
> +	[RPMH_PKA_CLK]		= &clk_rpmh_pka.hw,
> +	[RPMH_HWKM_CLK]		= &clk_rpmh_hwkm.hw,
> +};
> +
> +static const struct clk_rpmh_desc clk_rpmh_sa8775p = {
> +	.clks = sa8775p_rpmh_clocks,
> +	.num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks),
> +};
> +
>  static struct clk_hw *sdm670_rpmh_clocks[] = {
>  	[RPMH_CXO_CLK]		= &clk_rpmh_bi_tcxo_div2.hw,
>  	[RPMH_CXO_CLK_A]	= &clk_rpmh_bi_tcxo_div2_ao.hw,
> @@ -730,6 +746,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
>  
>  static const struct of_device_id clk_rpmh_match_table[] = {
>  	{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
> +	{ .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p},
>  	{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
>  	{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
>  	{ .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Shazad Hussain <quic_shazhuss@quicinc.com>
> 
> Introduce QTI SA8775P-specific interconnect driver.
> 
> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> [Bartosz: made the driver ready for upstream]
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  drivers/interconnect/qcom/Kconfig   |    9 +
>  drivers/interconnect/qcom/Makefile  |    2 +
>  drivers/interconnect/qcom/sa8775p.c | 2542 +++++++++++++++++++++++++++
>  3 files changed, 2553 insertions(+)
>  create mode 100644 drivers/interconnect/qcom/sa8775p.c
> 
> diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
> index 1a1c941635a2..023e42ebe365 100644
> --- a/drivers/interconnect/qcom/Kconfig
> +++ b/drivers/interconnect/qcom/Kconfig
> @@ -83,6 +83,15 @@ config INTERCONNECT_QCOM_RPMH_POSSIBLE
>  config INTERCONNECT_QCOM_RPMH
>  	tristate
>  
> +config INTERCONNECT_QCOM_SA8775P
> +	tristate "Qualcomm SA8775P interconnect driver"
> +	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
> +	select INTERCONNECT_QCOM_RPMH
> +	select INTERCONNECT_QCOM_BCM_VOTER
> +	help
> +	  This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
> +	  platforms.
> +
>  config INTERCONNECT_QCOM_SC7180
>  	tristate "Qualcomm SC7180 interconnect driver"
>  	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
> diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
> index 8e357528185d..32d90ff7960e 100644
> --- a/drivers/interconnect/qcom/Makefile
> +++ b/drivers/interconnect/qcom/Makefile
> @@ -12,6 +12,7 @@ icc-osm-l3-objs				:= osm-l3.o
>  qnoc-qcm2290-objs			:= qcm2290.o
>  qnoc-qcs404-objs			:= qcs404.o
>  icc-rpmh-obj				:= icc-rpmh.o
> +qnoc-sa8775p-objs			:= sa8775p.o
>  qnoc-sc7180-objs			:= sc7180.o
>  qnoc-sc7280-objs                        := sc7280.o
>  qnoc-sc8180x-objs			:= sc8180x.o
> @@ -36,6 +37,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
>  obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
>  obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
>  obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
> +obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o
>  obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
>  obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
>  obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
> diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
> new file mode 100644
> index 000000000000..bb23234eaad5
> --- /dev/null
> +++ b/drivers/interconnect/qcom/sa8775p.c
> @@ -0,0 +1,2542 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <linux/device.h>
> +#include <linux/interconnect.h>
> +#include <linux/interconnect-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
> +
> +#include "bcm-voter.h"
> +#include "icc-rpmh.h"
> +
> +#define LEMANS_MASTER_GPU_TCU				0
s/LEMANS/SA8775P; Qualcomm codenames are not really deterministic
and hence we use the numeric names upstream.

Konrad
> +#define LEMANS_MASTER_PCIE_TCU				1
> +#define LEMANS_MASTER_SYS_TCU				2
> +#define LEMANS_MASTER_APPSS_PROC			3
> +#define LEMANS_MASTER_LLCC				4
> +#define LEMANS_MASTER_CNOC_LPASS_AG_NOC			5
> +#define LEMANS_MASTER_GIC_AHB				6
> +#define LEMANS_MASTER_CDSP_NOC_CFG			7
> +#define LEMANS_MASTER_CDSPB_NOC_CFG			8
> +#define LEMANS_MASTER_QDSS_BAM				9
> +#define LEMANS_MASTER_QUP_0				10
> +#define LEMANS_MASTER_QUP_1				11
> +#define LEMANS_MASTER_QUP_2				12
> +#define LEMANS_MASTER_A1NOC_SNOC			13
> +#define LEMANS_MASTER_A2NOC_SNOC			14
> +#define LEMANS_MASTER_CAMNOC_HF				15
> +#define LEMANS_MASTER_CAMNOC_ICP			16
> +#define LEMANS_MASTER_CAMNOC_SF				17
> +#define LEMANS_MASTER_COMPUTE_NOC			18
> +#define LEMANS_MASTER_COMPUTE_NOC_1			19
> +#define LEMANS_MASTER_CNOC_A2NOC			20
> +#define LEMANS_MASTER_CNOC_DC_NOC			21
> +#define LEMANS_MASTER_GEM_NOC_CFG			22
> +#define LEMANS_MASTER_GEM_NOC_CNOC			23
> +#define LEMANS_MASTER_GEM_NOC_PCIE_SNOC			24
> +#define LEMANS_MASTER_GPDSP_SAIL			25
> +#define LEMANS_MASTER_GFX3D				26
> +#define LEMANS_MASTER_LPASS_ANOC			27
> +#define LEMANS_MASTER_MDP0				28
> +#define LEMANS_MASTER_MDP1				29
> +#define LEMANS_MASTER_MDP_CORE1_0			30
> +#define LEMANS_MASTER_MDP_CORE1_1			31
> +#define LEMANS_MASTER_MNOC_HF_MEM_NOC			32
> +#define LEMANS_MASTER_CNOC_MNOC_HF_CFG			33
> +#define LEMANS_MASTER_MNOC_SF_MEM_NOC			34
> +#define LEMANS_MASTER_CNOC_MNOC_SF_CFG			35
> +#define LEMANS_MASTER_ANOC_PCIE_GEM_NOC			36
> +#define LEMANS_MASTER_SNOC_CFG				37
> +#define LEMANS_MASTER_SNOC_GC_MEM_NOC			38
> +#define LEMANS_MASTER_SNOC_SF_MEM_NOC			39
> +#define LEMANS_MASTER_VIDEO_P0				40
> +#define LEMANS_MASTER_VIDEO_P1				41
> +#define LEMANS_MASTER_VIDEO_PROC			42
> +#define LEMANS_MASTER_VIDEO_V_PROC			43
> +#define LEMANS_MASTER_QUP_CORE_0			44
> +#define LEMANS_MASTER_QUP_CORE_1			45
> +#define LEMANS_MASTER_QUP_CORE_2			46
> +#define LEMANS_MASTER_QUP_CORE_3			47
> +#define LEMANS_MASTER_CRYPTO_CORE0			48
> +#define LEMANS_MASTER_CRYPTO_CORE1			49
> +#define LEMANS_MASTER_DSP0				50
> +#define LEMANS_MASTER_DSP1				51
> +#define LEMANS_MASTER_IPA				52
> +#define LEMANS_MASTER_LPASS_PROC			53
> +#define LEMANS_MASTER_CDSP_PROC				54
> +#define LEMANS_MASTER_CDSP_PROC_B			55
> +#define LEMANS_MASTER_PIMEM				56
> +#define LEMANS_MASTER_QUP_3				57
> +#define LEMANS_MASTER_EMAC				58
> +#define LEMANS_MASTER_EMAC_1				59
> +#define LEMANS_MASTER_GIC				60
> +#define LEMANS_MASTER_PCIE_0				61
> +#define LEMANS_MASTER_PCIE_1				62
> +#define LEMANS_MASTER_QDSS_ETR_0			63
> +#define LEMANS_MASTER_QDSS_ETR_1			64
> +#define LEMANS_MASTER_SDC				65
> +#define LEMANS_MASTER_UFS_CARD				66
> +#define LEMANS_MASTER_UFS_MEM				67
> +#define LEMANS_MASTER_USB2				68
> +#define LEMANS_MASTER_USB3_0				69
> +#define LEMANS_MASTER_USB3_1				70
> +#define LEMANS_SLAVE_EBI1				512
> +#define LEMANS_SLAVE_AHB2PHY_0				513
> +#define LEMANS_SLAVE_AHB2PHY_1				514
> +#define LEMANS_SLAVE_AHB2PHY_2				515
> +#define LEMANS_SLAVE_AHB2PHY_3				516
> +#define LEMANS_SLAVE_ANOC_THROTTLE_CFG			517
> +#define LEMANS_SLAVE_AOSS				518
> +#define LEMANS_SLAVE_APPSS				519
> +#define LEMANS_SLAVE_BOOT_ROM				520
> +#define LEMANS_SLAVE_CAMERA_CFG				521
> +#define LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG		522
> +#define LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG		523
> +#define LEMANS_SLAVE_CLK_CTL				524
> +#define LEMANS_SLAVE_CDSP_CFG				525
> +#define LEMANS_SLAVE_CDSP1_CFG				526
> +#define LEMANS_SLAVE_RBCPR_CX_CFG			527
> +#define LEMANS_SLAVE_RBCPR_MMCX_CFG			528
> +#define LEMANS_SLAVE_RBCPR_MX_CFG			529
> +#define LEMANS_SLAVE_CPR_NSPCX				530
> +#define LEMANS_SLAVE_CRYPTO_0_CFG			531
> +#define LEMANS_SLAVE_CX_RDPM				532
> +#define LEMANS_SLAVE_DISPLAY_CFG			533
> +#define LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG		534
> +#define LEMANS_SLAVE_DISPLAY1_CFG			535
> +#define LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG		536
> +#define LEMANS_SLAVE_EMAC_CFG				537
> +#define LEMANS_SLAVE_EMAC1_CFG				538
> +#define LEMANS_SLAVE_GP_DSP0_CFG			539
> +#define LEMANS_SLAVE_GP_DSP1_CFG			540
> +#define LEMANS_SLAVE_GPDSP0_THROTTLE_CFG		541
> +#define LEMANS_SLAVE_GPDSP1_THROTTLE_CFG		542
> +#define LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG		543
> +#define LEMANS_SLAVE_GFX3D_CFG				544
> +#define LEMANS_SLAVE_HWKM				545
> +#define LEMANS_SLAVE_IMEM_CFG				546
> +#define LEMANS_SLAVE_IPA_CFG				547
> +#define LEMANS_SLAVE_IPC_ROUTER_CFG			548
> +#define LEMANS_SLAVE_LLCC_CFG				549
> +#define LEMANS_SLAVE_LPASS				550
> +#define LEMANS_SLAVE_LPASS_CORE_CFG			551
> +#define LEMANS_SLAVE_LPASS_LPI_CFG			552
> +#define LEMANS_SLAVE_LPASS_MPU_CFG			553
> +#define LEMANS_SLAVE_LPASS_THROTTLE_CFG			554
> +#define LEMANS_SLAVE_LPASS_TOP_CFG			555
> +#define LEMANS_SLAVE_MX_RDPM				556
> +#define LEMANS_SLAVE_MXC_RDPM				557
> +#define LEMANS_SLAVE_PCIE_0_CFG				558
> +#define LEMANS_SLAVE_PCIE_1_CFG				559
> +#define LEMANS_SLAVE_PCIE_RSC_CFG			560
> +#define LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG		561
> +#define LEMANS_SLAVE_PCIE_THROTTLE_CFG			562
> +#define LEMANS_SLAVE_PDM				563
> +#define LEMANS_SLAVE_PIMEM_CFG				564
> +#define LEMANS_SLAVE_PKA_WRAPPER_CFG			565
> +#define LEMANS_SLAVE_QDSS_CFG				566
> +#define LEMANS_SLAVE_QM_CFG				567
> +#define LEMANS_SLAVE_QM_MPU_CFG				568
> +#define LEMANS_SLAVE_QUP_0				569
> +#define LEMANS_SLAVE_QUP_1				570
> +#define LEMANS_SLAVE_QUP_2				571
> +#define LEMANS_SLAVE_QUP_3				572
> +#define LEMANS_SLAVE_SAIL_THROTTLE_CFG			573
> +#define LEMANS_SLAVE_SDC1				574
> +#define LEMANS_SLAVE_SECURITY				575
> +#define LEMANS_SLAVE_SNOC_THROTTLE_CFG			576
> +#define LEMANS_SLAVE_TCSR				577
> +#define LEMANS_SLAVE_TLMM				578
> +#define LEMANS_SLAVE_TSC_CFG				579
> +#define LEMANS_SLAVE_UFS_CARD_CFG			580
> +#define LEMANS_SLAVE_UFS_MEM_CFG			581
> +#define LEMANS_SLAVE_USB2				582
> +#define LEMANS_SLAVE_USB3_0				583
> +#define LEMANS_SLAVE_USB3_1				584
> +#define LEMANS_SLAVE_VENUS_CFG				585
> +#define LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG		586
> +#define LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG		587
> +#define LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG		588
> +#define LEMANS_SLAVE_A1NOC_SNOC				589
> +#define LEMANS_SLAVE_A2NOC_SNOC				590
> +#define LEMANS_SLAVE_DDRSS_CFG				591
> +#define LEMANS_SLAVE_GEM_NOC_CNOC			592
> +#define LEMANS_SLAVE_GEM_NOC_CFG			593
> +#define LEMANS_SLAVE_SNOC_GEM_NOC_GC			594
> +#define LEMANS_SLAVE_SNOC_GEM_NOC_SF			595
> +#define LEMANS_SLAVE_GP_DSP_SAIL_NOC			596
> +#define LEMANS_SLAVE_GPDSP_NOC_CFG			597
> +#define LEMANS_SLAVE_HCP_A				598
> +#define LEMANS_SLAVE_LLCC				599
> +#define LEMANS_SLAVE_MNOC_HF_MEM_NOC			600
> +#define LEMANS_SLAVE_MNOC_SF_MEM_NOC			601
> +#define LEMANS_SLAVE_CNOC_MNOC_HF_CFG			602
> +#define LEMANS_SLAVE_CNOC_MNOC_SF_CFG			603
> +#define LEMANS_SLAVE_CDSP_MEM_NOC			604
> +#define LEMANS_SLAVE_CDSPB_MEM_NOC			605
> +#define LEMANS_SLAVE_HCP_B				606
> +#define LEMANS_SLAVE_GEM_NOC_PCIE_CNOC			607
> +#define LEMANS_SLAVE_PCIE_ANOC_CFG			608
> +#define LEMANS_SLAVE_ANOC_PCIE_GEM_NOC			609
> +#define LEMANS_SLAVE_SNOC_CFG				610
> +#define LEMANS_SLAVE_LPASS_SNOC				611
> +#define LEMANS_SLAVE_QUP_CORE_0				612
> +#define LEMANS_SLAVE_QUP_CORE_1				613
> +#define LEMANS_SLAVE_QUP_CORE_2				614
> +#define LEMANS_SLAVE_QUP_CORE_3				615
> +#define LEMANS_SLAVE_BOOT_IMEM				616
> +#define LEMANS_SLAVE_IMEM				617
> +#define LEMANS_SLAVE_PIMEM				618
> +#define LEMANS_SLAVE_SERVICE_NSP_NOC			619
> +#define LEMANS_SLAVE_SERVICE_NSPB_NOC			620
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC_1			621
> +#define LEMANS_SLAVE_SERVICE_MNOC_HF			622
> +#define LEMANS_SLAVE_SERVICE_MNOC_SF			623
> +#define LEMANS_SLAVE_SERVICES_LPASS_AML_NOC		624
> +#define LEMANS_SLAVE_SERVICE_LPASS_AG_NOC		625
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC_2			626
> +#define LEMANS_SLAVE_SERVICE_SNOC			627
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC			628
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC2			629
> +#define LEMANS_SLAVE_PCIE_0				630
> +#define LEMANS_SLAVE_PCIE_1				631
> +#define LEMANS_SLAVE_QDSS_STM				632
> +#define LEMANS_SLAVE_TCU				633
> +
> +static struct qcom_icc_node qxm_qup3 = {
> +	.name = "qxm_qup3",
> +	.id = LEMANS_MASTER_QUP_3,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_emac_0 = {
> +	.name = "xm_emac_0",
> +	.id = LEMANS_MASTER_EMAC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_emac_1 = {
> +	.name = "xm_emac_1",
> +	.id = LEMANS_MASTER_EMAC_1,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_sdc1 = {
> +	.name = "xm_sdc1",
> +	.id = LEMANS_MASTER_SDC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_ufs_mem = {
> +	.name = "xm_ufs_mem",
> +	.id = LEMANS_MASTER_UFS_MEM,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_usb2_2 = {
> +	.name = "xm_usb2_2",
> +	.id = LEMANS_MASTER_USB2,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_usb3_0 = {
> +	.name = "xm_usb3_0",
> +	.id = LEMANS_MASTER_USB3_0,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_usb3_1 = {
> +	.name = "xm_usb3_1",
> +	.id = LEMANS_MASTER_USB3_1,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qdss_bam = {
> +	.name = "qhm_qdss_bam",
> +	.id = LEMANS_MASTER_QDSS_BAM,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qup0 = {
> +	.name = "qhm_qup0",
> +	.id = LEMANS_MASTER_QUP_0,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qup1 = {
> +	.name = "qhm_qup1",
> +	.id = LEMANS_MASTER_QUP_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qup2 = {
> +	.name = "qhm_qup2",
> +	.id = LEMANS_MASTER_QUP_2,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qnm_cnoc_datapath = {
> +	.name = "qnm_cnoc_datapath",
> +	.id = LEMANS_MASTER_CNOC_A2NOC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_crypto_0 = {
> +	.name = "qxm_crypto_0",
> +	.id = LEMANS_MASTER_CRYPTO_CORE0,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_crypto_1 = {
> +	.name = "qxm_crypto_1",
> +	.id = LEMANS_MASTER_CRYPTO_CORE1,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_ipa = {
> +	.name = "qxm_ipa",
> +	.id = LEMANS_MASTER_IPA,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_qdss_etr_0 = {
> +	.name = "xm_qdss_etr_0",
> +	.id = LEMANS_MASTER_QDSS_ETR_0,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_qdss_etr_1 = {
> +	.name = "xm_qdss_etr_1",
> +	.id = LEMANS_MASTER_QDSS_ETR_1,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_ufs_card = {
> +	.name = "xm_ufs_card",
> +	.id = LEMANS_MASTER_UFS_CARD,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qup0_core_master = {
> +	.name = "qup0_core_master",
> +	.id = LEMANS_MASTER_QUP_CORE_0,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_QUP_CORE_0 },
> +};
> +
> +static struct qcom_icc_node qup1_core_master = {
> +	.name = "qup1_core_master",
> +	.id = LEMANS_MASTER_QUP_CORE_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_QUP_CORE_1 },
> +};
> +
> +static struct qcom_icc_node qup2_core_master = {
> +	.name = "qup2_core_master",
> +	.id = LEMANS_MASTER_QUP_CORE_2,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_QUP_CORE_2 },
> +};
> +
> +static struct qcom_icc_node qup3_core_master = {
> +	.name = "qup3_core_master",
> +	.id = LEMANS_MASTER_QUP_CORE_3,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_QUP_CORE_3 },
> +};
> +
> +static struct qcom_icc_node qnm_gemnoc_cnoc = {
> +	.name = "qnm_gemnoc_cnoc",
> +	.id = LEMANS_MASTER_GEM_NOC_CNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 82,
> +	.links = { LEMANS_SLAVE_AHB2PHY_0,
> +			   LEMANS_SLAVE_AHB2PHY_1,
> +		       LEMANS_SLAVE_AHB2PHY_2,
> +			   LEMANS_SLAVE_AHB2PHY_3,
> +			   LEMANS_SLAVE_ANOC_THROTTLE_CFG,
> +			   LEMANS_SLAVE_AOSS,
> +			   LEMANS_SLAVE_APPSS,
> +			   LEMANS_SLAVE_BOOT_ROM,
> +			   LEMANS_SLAVE_CAMERA_CFG,
> +			   LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG,
> +			   LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG,
> +			   LEMANS_SLAVE_CLK_CTL,
> +			   LEMANS_SLAVE_CDSP_CFG,
> +			   LEMANS_SLAVE_CDSP1_CFG,
> +			   LEMANS_SLAVE_RBCPR_CX_CFG,
> +			   LEMANS_SLAVE_RBCPR_MMCX_CFG,
> +			   LEMANS_SLAVE_RBCPR_MX_CFG,
> +			   LEMANS_SLAVE_CPR_NSPCX,
> +			   LEMANS_SLAVE_CRYPTO_0_CFG,
> +			   LEMANS_SLAVE_CX_RDPM,
> +			   LEMANS_SLAVE_DISPLAY_CFG,
> +			   LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG,
> +			   LEMANS_SLAVE_DISPLAY1_CFG,
> +			   LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
> +			   LEMANS_SLAVE_EMAC_CFG,
> +			   LEMANS_SLAVE_EMAC1_CFG,
> +			   LEMANS_SLAVE_GP_DSP0_CFG,
> +			   LEMANS_SLAVE_GP_DSP1_CFG,
> +			   LEMANS_SLAVE_GPDSP0_THROTTLE_CFG,
> +			   LEMANS_SLAVE_GPDSP1_THROTTLE_CFG,
> +			   LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG,
> +			   LEMANS_SLAVE_GFX3D_CFG,
> +			   LEMANS_SLAVE_HWKM,
> +			   LEMANS_SLAVE_IMEM_CFG,
> +			   LEMANS_SLAVE_IPA_CFG,
> +			   LEMANS_SLAVE_IPC_ROUTER_CFG,
> +			   LEMANS_SLAVE_LPASS,
> +			   LEMANS_SLAVE_LPASS_THROTTLE_CFG,
> +			   LEMANS_SLAVE_MX_RDPM,
> +			   LEMANS_SLAVE_MXC_RDPM,
> +			   LEMANS_SLAVE_PCIE_0_CFG,
> +			   LEMANS_SLAVE_PCIE_1_CFG,
> +			   LEMANS_SLAVE_PCIE_RSC_CFG,
> +			   LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG,
> +			   LEMANS_SLAVE_PCIE_THROTTLE_CFG,
> +			   LEMANS_SLAVE_PDM,
> +			   LEMANS_SLAVE_PIMEM_CFG,
> +			   LEMANS_SLAVE_PKA_WRAPPER_CFG,
> +			   LEMANS_SLAVE_QDSS_CFG,
> +			   LEMANS_SLAVE_QM_CFG,
> +			   LEMANS_SLAVE_QM_MPU_CFG,
> +			   LEMANS_SLAVE_QUP_0,
> +			   LEMANS_SLAVE_QUP_1,
> +			   LEMANS_SLAVE_QUP_2,
> +			   LEMANS_SLAVE_QUP_3,
> +			   LEMANS_SLAVE_SAIL_THROTTLE_CFG,
> +			   LEMANS_SLAVE_SDC1,
> +			   LEMANS_SLAVE_SECURITY,
> +			   LEMANS_SLAVE_SNOC_THROTTLE_CFG,
> +			   LEMANS_SLAVE_TCSR,
> +			   LEMANS_SLAVE_TLMM,
> +			   LEMANS_SLAVE_TSC_CFG,
> +			   LEMANS_SLAVE_UFS_CARD_CFG,
> +			   LEMANS_SLAVE_UFS_MEM_CFG,
> +			   LEMANS_SLAVE_USB2,
> +			   LEMANS_SLAVE_USB3_0,
> +			   LEMANS_SLAVE_USB3_1,
> +			   LEMANS_SLAVE_VENUS_CFG,
> +			   LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG,
> +			   LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
> +			   LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
> +			   LEMANS_SLAVE_DDRSS_CFG,
> +			   LEMANS_SLAVE_GPDSP_NOC_CFG,
> +			   LEMANS_SLAVE_CNOC_MNOC_HF_CFG,
> +			   LEMANS_SLAVE_CNOC_MNOC_SF_CFG,
> +			   LEMANS_SLAVE_PCIE_ANOC_CFG,
> +			   LEMANS_SLAVE_SNOC_CFG,
> +			   LEMANS_SLAVE_BOOT_IMEM,
> +			   LEMANS_SLAVE_IMEM,
> +			   LEMANS_SLAVE_PIMEM,
> +			   LEMANS_SLAVE_QDSS_STM,
> +			   LEMANS_SLAVE_TCU
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_gemnoc_pcie = {
> +	.name = "qnm_gemnoc_pcie",
> +	.id = LEMANS_MASTER_GEM_NOC_PCIE_SNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_PCIE_0,
> +		   LEMANS_SLAVE_PCIE_1
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_cnoc_dc_noc = {
> +	.name = "qnm_cnoc_dc_noc",
> +	.id = LEMANS_MASTER_CNOC_DC_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_LLCC_CFG,
> +		   LEMANS_SLAVE_GEM_NOC_CFG
> +	},
> +};
> +
> +static struct qcom_icc_node alm_gpu_tcu = {
> +	.name = "alm_gpu_tcu",
> +	.id = LEMANS_MASTER_GPU_TCU,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node alm_pcie_tcu = {
> +	.name = "alm_pcie_tcu",
> +	.id = LEMANS_MASTER_PCIE_TCU,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node alm_sys_tcu = {
> +	.name = "alm_sys_tcu",
> +	.id = LEMANS_MASTER_SYS_TCU,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node chm_apps = {
> +	.name = "chm_apps",
> +	.id = LEMANS_MASTER_APPSS_PROC,
> +	.channels = 4,
> +	.buswidth = 32,
> +	.num_links = 3,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC,
> +		   LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_cmpnoc0 = {
> +	.name = "qnm_cmpnoc0",
> +	.id = LEMANS_MASTER_COMPUTE_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_cmpnoc1 = {
> +	.name = "qnm_cmpnoc1",
> +	.id = LEMANS_MASTER_COMPUTE_NOC_1,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_gemnoc_cfg = {
> +	.name = "qnm_gemnoc_cfg",
> +	.id = LEMANS_MASTER_GEM_NOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 4,
> +	.links = { LEMANS_SLAVE_SERVICE_GEM_NOC_1,
> +		   LEMANS_SLAVE_SERVICE_GEM_NOC_2,
> +		   LEMANS_SLAVE_SERVICE_GEM_NOC,
> +		   LEMANS_SLAVE_SERVICE_GEM_NOC2
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_gpdsp_sail = {
> +	.name = "qnm_gpdsp_sail",
> +	.id = LEMANS_MASTER_GPDSP_SAIL,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_gpu = {
> +	.name = "qnm_gpu",
> +	.id = LEMANS_MASTER_GFX3D,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_hf = {
> +	.name = "qnm_mnoc_hf",
> +	.id = LEMANS_MASTER_MNOC_HF_MEM_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_LLCC,
> +		   LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_sf = {
> +	.name = "qnm_mnoc_sf",
> +	.id = LEMANS_MASTER_MNOC_SF_MEM_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 3,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC,
> +		   LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_pcie = {
> +	.name = "qnm_pcie",
> +	.id = LEMANS_MASTER_ANOC_PCIE_GEM_NOC,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC
> +	},
> +};
> +
> +static struct qcom_icc_node qnm_snoc_gc = {
> +	.name = "qnm_snoc_gc",
> +	.id = LEMANS_MASTER_SNOC_GC_MEM_NOC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_LLCC },
> +};
> +
> +static struct qcom_icc_node qnm_snoc_sf = {
> +	.name = "qnm_snoc_sf",
> +	.id = LEMANS_MASTER_SNOC_SF_MEM_NOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 3,
> +	.links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> +		   LEMANS_SLAVE_LLCC,
> +		   LEMANS_SLAVE_GEM_NOC_PCIE_CNOC },
> +};
> +
> +static struct qcom_icc_node qxm_dsp0 = {
> +	.name = "qxm_dsp0",
> +	.id = LEMANS_MASTER_DSP0,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_GP_DSP_SAIL_NOC },
> +};
> +
> +static struct qcom_icc_node qxm_dsp1 = {
> +	.name = "qxm_dsp1",
> +	.id = LEMANS_MASTER_DSP1,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_GP_DSP_SAIL_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_config_noc = {
> +	.name = "qhm_config_noc",
> +	.id = LEMANS_MASTER_CNOC_LPASS_AG_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 6,
> +	.links = { LEMANS_SLAVE_LPASS_CORE_CFG,
> +		   LEMANS_SLAVE_LPASS_LPI_CFG,
> +		   LEMANS_SLAVE_LPASS_MPU_CFG,
> +		   LEMANS_SLAVE_LPASS_TOP_CFG,
> +		   LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
> +		   LEMANS_SLAVE_SERVICE_LPASS_AG_NOC
> +	},
> +};
> +
> +static struct qcom_icc_node qxm_lpass_dsp = {
> +	.name = "qxm_lpass_dsp",
> +	.id = LEMANS_MASTER_LPASS_PROC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 4,
> +	.links = { LEMANS_SLAVE_LPASS_TOP_CFG,
> +		   LEMANS_SLAVE_LPASS_SNOC,
> +		   LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
> +		   LEMANS_SLAVE_SERVICE_LPASS_AG_NOC
> +	},
> +};
> +
> +static struct qcom_icc_node llcc_mc = {
> +	.name = "llcc_mc",
> +	.id = LEMANS_MASTER_LLCC,
> +	.channels = 8,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_EBI1 },
> +};
> +
> +static struct qcom_icc_node qnm_camnoc_hf = {
> +	.name = "qnm_camnoc_hf",
> +	.id = LEMANS_MASTER_CAMNOC_HF,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_camnoc_icp = {
> +	.name = "qnm_camnoc_icp",
> +	.id = LEMANS_MASTER_CAMNOC_ICP,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_camnoc_sf = {
> +	.name = "qnm_camnoc_sf",
> +	.id = LEMANS_MASTER_CAMNOC_SF,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp0_0 = {
> +	.name = "qnm_mdp0_0",
> +	.id = LEMANS_MASTER_MDP0,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp0_1 = {
> +	.name = "qnm_mdp0_1",
> +	.id = LEMANS_MASTER_MDP1,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp1_0 = {
> +	.name = "qnm_mdp1_0",
> +	.id = LEMANS_MASTER_MDP_CORE1_0,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp1_1 = {
> +	.name = "qnm_mdp1_1",
> +	.id = LEMANS_MASTER_MDP_CORE1_1,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_hf_cfg = {
> +	.name = "qnm_mnoc_hf_cfg",
> +	.id = LEMANS_MASTER_CNOC_MNOC_HF_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SERVICE_MNOC_HF },
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_sf_cfg = {
> +	.name = "qnm_mnoc_sf_cfg",
> +	.id = LEMANS_MASTER_CNOC_MNOC_SF_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SERVICE_MNOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_video0 = {
> +	.name = "qnm_video0",
> +	.id = LEMANS_MASTER_VIDEO_P0,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_video1 = {
> +	.name = "qnm_video1",
> +	.id = LEMANS_MASTER_VIDEO_P1,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_video_cvp = {
> +	.name = "qnm_video_cvp",
> +	.id = LEMANS_MASTER_VIDEO_PROC,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_video_v_cpu = {
> +	.name = "qnm_video_v_cpu",
> +	.id = LEMANS_MASTER_VIDEO_V_PROC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_nsp_noc_config = {
> +	.name = "qhm_nsp_noc_config",
> +	.id = LEMANS_MASTER_CDSP_NOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SERVICE_NSP_NOC },
> +};
> +
> +static struct qcom_icc_node qxm_nsp = {
> +	.name = "qxm_nsp",
> +	.id = LEMANS_MASTER_CDSP_PROC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_nspb_noc_config = {
> +	.name = "qhm_nspb_noc_config",
> +	.id = LEMANS_MASTER_CDSPB_NOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SERVICE_NSPB_NOC },
> +};
> +
> +static struct qcom_icc_node qxm_nspb = {
> +	.name = "qxm_nspb",
> +	.id = LEMANS_MASTER_CDSP_PROC_B,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 2,
> +	.links = { LEMANS_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node xm_pcie3_0 = {
> +	.name = "xm_pcie3_0",
> +	.id = LEMANS_MASTER_PCIE_0,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_ANOC_PCIE_GEM_NOC },
> +};
> +
> +static struct qcom_icc_node xm_pcie3_1 = {
> +	.name = "xm_pcie3_1",
> +	.id = LEMANS_MASTER_PCIE_1,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_ANOC_PCIE_GEM_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_gic = {
> +	.name = "qhm_gic",
> +	.id = LEMANS_MASTER_GIC_AHB,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_aggre1_noc = {
> +	.name = "qnm_aggre1_noc",
> +	.id = LEMANS_MASTER_A1NOC_SNOC,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_aggre2_noc = {
> +	.name = "qnm_aggre2_noc",
> +	.id = LEMANS_MASTER_A2NOC_SNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_lpass_noc = {
> +	.name = "qnm_lpass_noc",
> +	.id = LEMANS_MASTER_LPASS_ANOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_snoc_cfg = {
> +	.name = "qnm_snoc_cfg",
> +	.id = LEMANS_MASTER_SNOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SERVICE_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_pimem = {
> +	.name = "qxm_pimem",
> +	.id = LEMANS_MASTER_PIMEM,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SNOC_GEM_NOC_GC },
> +};
> +
> +static struct qcom_icc_node xm_gic = {
> +	.name = "xm_gic",
> +	.id = LEMANS_MASTER_GIC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_SLAVE_SNOC_GEM_NOC_GC },
> +};
> +
> +static struct qcom_icc_node qns_a1noc_snoc = {
> +	.name = "qns_a1noc_snoc",
> +	.id = LEMANS_SLAVE_A1NOC_SNOC,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qns_a2noc_snoc = {
> +	.name = "qns_a2noc_snoc",
> +	.id = LEMANS_SLAVE_A2NOC_SNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qup0_core_slave = {
> +	.name = "qup0_core_slave",
> +	.id = LEMANS_SLAVE_QUP_CORE_0,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qup1_core_slave = {
> +	.name = "qup1_core_slave",
> +	.id = LEMANS_SLAVE_QUP_CORE_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qup2_core_slave = {
> +	.name = "qup2_core_slave",
> +	.id = LEMANS_SLAVE_QUP_CORE_2,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qup3_core_slave = {
> +	.name = "qup3_core_slave",
> +	.id = LEMANS_SLAVE_QUP_CORE_3,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy0 = {
> +	.name = "qhs_ahb2phy0",
> +	.id = LEMANS_SLAVE_AHB2PHY_0,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy1 = {
> +	.name = "qhs_ahb2phy1",
> +	.id = LEMANS_SLAVE_AHB2PHY_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy2 = {
> +	.name = "qhs_ahb2phy2",
> +	.id = LEMANS_SLAVE_AHB2PHY_2,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy3 = {
> +	.name = "qhs_ahb2phy3",
> +	.id = LEMANS_SLAVE_AHB2PHY_3,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_anoc_throttle_cfg = {
> +	.name = "qhs_anoc_throttle_cfg",
> +	.id = LEMANS_SLAVE_ANOC_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_aoss = {
> +	.name = "qhs_aoss",
> +	.id = LEMANS_SLAVE_AOSS,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_apss = {
> +	.name = "qhs_apss",
> +	.id = LEMANS_SLAVE_APPSS,
> +	.channels = 1,
> +	.buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qhs_boot_rom = {
> +	.name = "qhs_boot_rom",
> +	.id = LEMANS_SLAVE_BOOT_ROM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_camera_cfg = {
> +	.name = "qhs_camera_cfg",
> +	.id = LEMANS_SLAVE_CAMERA_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
> +	.name = "qhs_camera_nrt_throttle_cfg",
> +	.id = LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
> +	.name = "qhs_camera_rt_throttle_cfg",
> +	.id = LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_clk_ctl = {
> +	.name = "qhs_clk_ctl",
> +	.id = LEMANS_SLAVE_CLK_CTL,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_compute0_cfg = {
> +	.name = "qhs_compute0_cfg",
> +	.id = LEMANS_SLAVE_CDSP_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_CDSP_NOC_CFG },
> +};
> +
> +static struct qcom_icc_node qhs_compute1_cfg = {
> +	.name = "qhs_compute1_cfg",
> +	.id = LEMANS_SLAVE_CDSP1_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_CDSPB_NOC_CFG },
> +};
> +
> +static struct qcom_icc_node qhs_cpr_cx = {
> +	.name = "qhs_cpr_cx",
> +	.id = LEMANS_SLAVE_RBCPR_CX_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cpr_mmcx = {
> +	.name = "qhs_cpr_mmcx",
> +	.id = LEMANS_SLAVE_RBCPR_MMCX_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cpr_mx = {
> +	.name = "qhs_cpr_mx",
> +	.id = LEMANS_SLAVE_RBCPR_MX_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cpr_nspcx = {
> +	.name = "qhs_cpr_nspcx",
> +	.id = LEMANS_SLAVE_CPR_NSPCX,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_crypto0_cfg = {
> +	.name = "qhs_crypto0_cfg",
> +	.id = LEMANS_SLAVE_CRYPTO_0_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cx_rdpm = {
> +	.name = "qhs_cx_rdpm",
> +	.id = LEMANS_SLAVE_CX_RDPM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display0_cfg = {
> +	.name = "qhs_display0_cfg",
> +	.id = LEMANS_SLAVE_DISPLAY_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
> +	.name = "qhs_display0_rt_throttle_cfg",
> +	.id = LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display1_cfg = {
> +	.name = "qhs_display1_cfg",
> +	.id = LEMANS_SLAVE_DISPLAY1_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
> +	.name = "qhs_display1_rt_throttle_cfg",
> +	.id = LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_emac0_cfg = {
> +	.name = "qhs_emac0_cfg",
> +	.id = LEMANS_SLAVE_EMAC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_emac1_cfg = {
> +	.name = "qhs_emac1_cfg",
> +	.id = LEMANS_SLAVE_EMAC1_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gp_dsp0_cfg = {
> +	.name = "qhs_gp_dsp0_cfg",
> +	.id = LEMANS_SLAVE_GP_DSP0_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gp_dsp1_cfg = {
> +	.name = "qhs_gp_dsp1_cfg",
> +	.id = LEMANS_SLAVE_GP_DSP1_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
> +	.name = "qhs_gpdsp0_throttle_cfg",
> +	.id = LEMANS_SLAVE_GPDSP0_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
> +	.name = "qhs_gpdsp1_throttle_cfg",
> +	.id = LEMANS_SLAVE_GPDSP1_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
> +	.name = "qhs_gpu_tcu_throttle_cfg",
> +	.id = LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpuss_cfg = {
> +	.name = "qhs_gpuss_cfg",
> +	.id = LEMANS_SLAVE_GFX3D_CFG,
> +	.channels = 1,
> +	.buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qhs_hwkm = {
> +	.name = "qhs_hwkm",
> +	.id = LEMANS_SLAVE_HWKM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_imem_cfg = {
> +	.name = "qhs_imem_cfg",
> +	.id = LEMANS_SLAVE_IMEM_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ipa = {
> +	.name = "qhs_ipa",
> +	.id = LEMANS_SLAVE_IPA_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ipc_router = {
> +	.name = "qhs_ipc_router",
> +	.id = LEMANS_SLAVE_IPC_ROUTER_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_cfg = {
> +	.name = "qhs_lpass_cfg",
> +	.id = LEMANS_SLAVE_LPASS,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_CNOC_LPASS_AG_NOC },
> +};
> +
> +static struct qcom_icc_node qhs_lpass_throttle_cfg = {
> +	.name = "qhs_lpass_throttle_cfg",
> +	.id = LEMANS_SLAVE_LPASS_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_mx_rdpm = {
> +	.name = "qhs_mx_rdpm",
> +	.id = LEMANS_SLAVE_MX_RDPM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_mxc_rdpm = {
> +	.name = "qhs_mxc_rdpm",
> +	.id = LEMANS_SLAVE_MXC_RDPM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie0_cfg = {
> +	.name = "qhs_pcie0_cfg",
> +	.id = LEMANS_SLAVE_PCIE_0_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie1_cfg = {
> +	.name = "qhs_pcie1_cfg",
> +	.id = LEMANS_SLAVE_PCIE_1_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie_rsc_cfg = {
> +	.name = "qhs_pcie_rsc_cfg",
> +	.id = LEMANS_SLAVE_PCIE_RSC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
> +	.name = "qhs_pcie_tcu_throttle_cfg",
> +	.id = LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie_throttle_cfg = {
> +	.name = "qhs_pcie_throttle_cfg",
> +	.id = LEMANS_SLAVE_PCIE_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pdm = {
> +	.name = "qhs_pdm",
> +	.id = LEMANS_SLAVE_PDM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pimem_cfg = {
> +	.name = "qhs_pimem_cfg",
> +	.id = LEMANS_SLAVE_PIMEM_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pke_wrapper_cfg = {
> +	.name = "qhs_pke_wrapper_cfg",
> +	.id = LEMANS_SLAVE_PKA_WRAPPER_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qdss_cfg = {
> +	.name = "qhs_qdss_cfg",
> +	.id = LEMANS_SLAVE_QDSS_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qm_cfg = {
> +	.name = "qhs_qm_cfg",
> +	.id = LEMANS_SLAVE_QM_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qm_mpu_cfg = {
> +	.name = "qhs_qm_mpu_cfg",
> +	.id = LEMANS_SLAVE_QM_MPU_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup0 = {
> +	.name = "qhs_qup0",
> +	.id = LEMANS_SLAVE_QUP_0,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup1 = {
> +	.name = "qhs_qup1",
> +	.id = LEMANS_SLAVE_QUP_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup2 = {
> +	.name = "qhs_qup2",
> +	.id = LEMANS_SLAVE_QUP_2,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup3 = {
> +	.name = "qhs_qup3",
> +	.id = LEMANS_SLAVE_QUP_3,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_sail_throttle_cfg = {
> +	.name = "qhs_sail_throttle_cfg",
> +	.id = LEMANS_SLAVE_SAIL_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_sdc1 = {
> +	.name = "qhs_sdc1",
> +	.id = LEMANS_SLAVE_SDC1,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_security = {
> +	.name = "qhs_security",
> +	.id = LEMANS_SLAVE_SECURITY,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_snoc_throttle_cfg = {
> +	.name = "qhs_snoc_throttle_cfg",
> +	.id = LEMANS_SLAVE_SNOC_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_tcsr = {
> +	.name = "qhs_tcsr",
> +	.id = LEMANS_SLAVE_TCSR,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_tlmm = {
> +	.name = "qhs_tlmm",
> +	.id = LEMANS_SLAVE_TLMM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_tsc_cfg = {
> +	.name = "qhs_tsc_cfg",
> +	.id = LEMANS_SLAVE_TSC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ufs_card_cfg = {
> +	.name = "qhs_ufs_card_cfg",
> +	.id = LEMANS_SLAVE_UFS_CARD_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ufs_mem_cfg = {
> +	.name = "qhs_ufs_mem_cfg",
> +	.id = LEMANS_SLAVE_UFS_MEM_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_usb2_0 = {
> +	.name = "qhs_usb2_0",
> +	.id = LEMANS_SLAVE_USB2,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_usb3_0 = {
> +	.name = "qhs_usb3_0",
> +	.id = LEMANS_SLAVE_USB3_0,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_usb3_1 = {
> +	.name = "qhs_usb3_1",
> +	.id = LEMANS_SLAVE_USB3_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_cfg = {
> +	.name = "qhs_venus_cfg",
> +	.id = LEMANS_SLAVE_VENUS_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
> +	.name = "qhs_venus_cvp_throttle_cfg",
> +	.id = LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
> +	.name = "qhs_venus_v_cpu_throttle_cfg",
> +	.id = LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
> +	.name = "qhs_venus_vcodec_throttle_cfg",
> +	.id = LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_ddrss_cfg = {
> +	.name = "qns_ddrss_cfg",
> +	.id = LEMANS_SLAVE_DDRSS_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_CNOC_DC_NOC },
> +};
> +
> +static struct qcom_icc_node qns_gpdsp_noc_cfg = {
> +	.name = "qns_gpdsp_noc_cfg",
> +	.id = LEMANS_SLAVE_GPDSP_NOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_mnoc_hf_cfg = {
> +	.name = "qns_mnoc_hf_cfg",
> +	.id = LEMANS_SLAVE_CNOC_MNOC_HF_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_CNOC_MNOC_HF_CFG },
> +};
> +
> +static struct qcom_icc_node qns_mnoc_sf_cfg = {
> +	.name = "qns_mnoc_sf_cfg",
> +	.id = LEMANS_SLAVE_CNOC_MNOC_SF_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_CNOC_MNOC_SF_CFG },
> +};
> +
> +static struct qcom_icc_node qns_pcie_anoc_cfg = {
> +	.name = "qns_pcie_anoc_cfg",
> +	.id = LEMANS_SLAVE_PCIE_ANOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_snoc_cfg = {
> +	.name = "qns_snoc_cfg",
> +	.id = LEMANS_SLAVE_SNOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_SNOC_CFG },
> +};
> +
> +static struct qcom_icc_node qxs_boot_imem = {
> +	.name = "qxs_boot_imem",
> +	.id = LEMANS_SLAVE_BOOT_IMEM,
> +	.channels = 1,
> +	.buswidth = 16,
> +};
> +
> +static struct qcom_icc_node qxs_imem = {
> +	.name = "qxs_imem",
> +	.id = LEMANS_SLAVE_IMEM,
> +	.channels = 1,
> +	.buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qxs_pimem = {
> +	.name = "qxs_pimem",
> +	.id = LEMANS_SLAVE_PIMEM,
> +	.channels = 1,
> +	.buswidth = 8,
> +};
> +
> +static struct qcom_icc_node xs_pcie_0 = {
> +	.name = "xs_pcie_0",
> +	.id = LEMANS_SLAVE_PCIE_0,
> +	.channels = 1,
> +	.buswidth = 16,
> +};
> +
> +static struct qcom_icc_node xs_pcie_1 = {
> +	.name = "xs_pcie_1",
> +	.id = LEMANS_SLAVE_PCIE_1,
> +	.channels = 1,
> +	.buswidth = 32,
> +};
> +
> +static struct qcom_icc_node xs_qdss_stm = {
> +	.name = "xs_qdss_stm",
> +	.id = LEMANS_SLAVE_QDSS_STM,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node xs_sys_tcu_cfg = {
> +	.name = "xs_sys_tcu_cfg",
> +	.id = LEMANS_SLAVE_TCU,
> +	.channels = 1,
> +	.buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qhs_llcc = {
> +	.name = "qhs_llcc",
> +	.id = LEMANS_SLAVE_LLCC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_gemnoc = {
> +	.name = "qns_gemnoc",
> +	.id = LEMANS_SLAVE_GEM_NOC_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_GEM_NOC_CFG },
> +};
> +
> +static struct qcom_icc_node qns_gem_noc_cnoc = {
> +	.name = "qns_gem_noc_cnoc",
> +	.id = LEMANS_SLAVE_GEM_NOC_CNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_GEM_NOC_CNOC },
> +};
> +
> +static struct qcom_icc_node qns_llcc = {
> +	.name = "qns_llcc",
> +	.id = LEMANS_SLAVE_LLCC,
> +	.channels = 6,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_LLCC },
> +};
> +
> +static struct qcom_icc_node qns_pcie = {
> +	.name = "qns_pcie",
> +	.id = LEMANS_SLAVE_GEM_NOC_PCIE_CNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_GEM_NOC_PCIE_SNOC },
> +};
> +
> +static struct qcom_icc_node srvc_even_gemnoc = {
> +	.name = "srvc_even_gemnoc",
> +	.id = LEMANS_SLAVE_SERVICE_GEM_NOC_1,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_odd_gemnoc = {
> +	.name = "srvc_odd_gemnoc",
> +	.id = LEMANS_SLAVE_SERVICE_GEM_NOC_2,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_sys_gemnoc = {
> +	.name = "srvc_sys_gemnoc",
> +	.id = LEMANS_SLAVE_SERVICE_GEM_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_sys_gemnoc_2 = {
> +	.name = "srvc_sys_gemnoc_2",
> +	.id = LEMANS_SLAVE_SERVICE_GEM_NOC2,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_gp_dsp_sail_noc = {
> +	.name = "qns_gp_dsp_sail_noc",
> +	.id = LEMANS_SLAVE_GP_DSP_SAIL_NOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_GPDSP_SAIL },
> +};
> +
> +static struct qcom_icc_node qhs_lpass_core = {
> +	.name = "qhs_lpass_core",
> +	.id = LEMANS_SLAVE_LPASS_CORE_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_lpi = {
> +	.name = "qhs_lpass_lpi",
> +	.id = LEMANS_SLAVE_LPASS_LPI_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_mpu = {
> +	.name = "qhs_lpass_mpu",
> +	.id = LEMANS_SLAVE_LPASS_MPU_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_top = {
> +	.name = "qhs_lpass_top",
> +	.id = LEMANS_SLAVE_LPASS_TOP_CFG,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_sysnoc = {
> +	.name = "qns_sysnoc",
> +	.id = LEMANS_SLAVE_LPASS_SNOC,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_LPASS_ANOC },
> +};
> +
> +static struct qcom_icc_node srvc_niu_aml_noc = {
> +	.name = "srvc_niu_aml_noc",
> +	.id = LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_niu_lpass_agnoc = {
> +	.name = "srvc_niu_lpass_agnoc",
> +	.id = LEMANS_SLAVE_SERVICE_LPASS_AG_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node ebi = {
> +	.name = "ebi",
> +	.id = LEMANS_SLAVE_EBI1,
> +	.channels = 8,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_mem_noc_hf = {
> +	.name = "qns_mem_noc_hf",
> +	.id = LEMANS_SLAVE_MNOC_HF_MEM_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qns_mem_noc_sf = {
> +	.name = "qns_mem_noc_sf",
> +	.id = LEMANS_SLAVE_MNOC_SF_MEM_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node srvc_mnoc_hf = {
> +	.name = "srvc_mnoc_hf",
> +	.id = LEMANS_SLAVE_SERVICE_MNOC_HF,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_mnoc_sf = {
> +	.name = "srvc_mnoc_sf",
> +	.id = LEMANS_SLAVE_SERVICE_MNOC_SF,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_hcp = {
> +	.name = "qns_hcp",
> +	.id = LEMANS_SLAVE_HCP_A,
> +	.channels = 2,
> +	.buswidth = 32,
> +};
> +
> +static struct qcom_icc_node qns_nsp_gemnoc = {
> +	.name = "qns_nsp_gemnoc",
> +	.id = LEMANS_SLAVE_CDSP_MEM_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_COMPUTE_NOC },
> +};
> +
> +static struct qcom_icc_node service_nsp_noc = {
> +	.name = "service_nsp_noc",
> +	.id = LEMANS_SLAVE_SERVICE_NSP_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_nspb_gemnoc = {
> +	.name = "qns_nspb_gemnoc",
> +	.id = LEMANS_SLAVE_CDSPB_MEM_NOC,
> +	.channels = 2,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_COMPUTE_NOC_1 },
> +};
> +
> +static struct qcom_icc_node qns_nspb_hcp = {
> +	.name = "qns_nspb_hcp",
> +	.id = LEMANS_SLAVE_HCP_B,
> +	.channels = 2,
> +	.buswidth = 32,
> +};
> +
> +static struct qcom_icc_node service_nspb_noc = {
> +	.name = "service_nspb_noc",
> +	.id = LEMANS_SLAVE_SERVICE_NSPB_NOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_pcie_mem_noc = {
> +	.name = "qns_pcie_mem_noc",
> +	.id = LEMANS_SLAVE_ANOC_PCIE_GEM_NOC,
> +	.channels = 1,
> +	.buswidth = 32,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_ANOC_PCIE_GEM_NOC },
> +};
> +
> +static struct qcom_icc_node qns_gemnoc_gc = {
> +	.name = "qns_gemnoc_gc",
> +	.id = LEMANS_SLAVE_SNOC_GEM_NOC_GC,
> +	.channels = 1,
> +	.buswidth = 8,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_SNOC_GC_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qns_gemnoc_sf = {
> +	.name = "qns_gemnoc_sf",
> +	.id = LEMANS_SLAVE_SNOC_GEM_NOC_SF,
> +	.channels = 1,
> +	.buswidth = 16,
> +	.num_links = 1,
> +	.links = { LEMANS_MASTER_SNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node srvc_snoc = {
> +	.name = "srvc_snoc",
> +	.id = LEMANS_SLAVE_SERVICE_SNOC,
> +	.channels = 1,
> +	.buswidth = 4,
> +};
> +
> +static struct qcom_icc_bcm bcm_acv = {
> +	.name = "ACV",
> +	.num_nodes = 1,
> +	.nodes = { &ebi },
> +};
> +
> +static struct qcom_icc_bcm bcm_ce0 = {
> +	.name = "CE0",
> +	.num_nodes = 2,
> +	.nodes = { &qxm_crypto_0, &qxm_crypto_1 },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn0 = {
> +	.name = "CN0",
> +	.keepalive = true,
> +	.num_nodes = 2,
> +	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn1 = {
> +	.name = "CN1",
> +	.num_nodes = 76,
> +	.nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
> +		   &qhs_ahb2phy2, &qhs_ahb2phy3,
> +		   &qhs_anoc_throttle_cfg, &qhs_aoss,
> +		   &qhs_apss, &qhs_boot_rom,
> +		   &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
> +		   &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
> +		   &qhs_compute0_cfg, &qhs_compute1_cfg,
> +		   &qhs_cpr_cx, &qhs_cpr_mmcx,
> +		   &qhs_cpr_mx, &qhs_cpr_nspcx,
> +		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
> +		   &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
> +		   &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
> +		   &qhs_emac0_cfg, &qhs_emac1_cfg,
> +		   &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
> +		   &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
> +		   &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
> +		   &qhs_hwkm, &qhs_imem_cfg,
> +		   &qhs_ipa, &qhs_ipc_router,
> +		   &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
> +		   &qhs_mx_rdpm, &qhs_mxc_rdpm,
> +		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
> +		   &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
> +		   &qhs_pcie_throttle_cfg, &qhs_pdm,
> +		   &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
> +		   &qhs_qdss_cfg, &qhs_qm_cfg,
> +		   &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
> +		   &qhs_sdc1, &qhs_security,
> +		   &qhs_snoc_throttle_cfg, &qhs_tcsr,
> +		   &qhs_tlmm, &qhs_tsc_cfg,
> +		   &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
> +		   &qhs_usb2_0, &qhs_usb3_0,
> +		   &qhs_usb3_1, &qhs_venus_cfg,
> +		   &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
> +		   &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
> +		   &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
> +		   &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
> +		   &qns_snoc_cfg, &qxs_boot_imem,
> +		   &qxs_imem, &xs_sys_tcu_cfg },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn2 = {
> +	.name = "CN2",
> +	.num_nodes = 4,
> +	.nodes = { &qhs_qup0, &qhs_qup1,
> +		   &qhs_qup2, &qhs_qup3 },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn3 = {
> +	.name = "CN3",
> +	.num_nodes = 2,
> +	.nodes = { &xs_pcie_0, &xs_pcie_1 },
> +};
> +
> +static struct qcom_icc_bcm bcm_gna0 = {
> +	.name = "GNA0",
> +	.num_nodes = 1,
> +	.nodes = { &qxm_dsp0 },
> +};
> +
> +static struct qcom_icc_bcm bcm_gnb0 = {
> +	.name = "GNB0",
> +	.num_nodes = 1,
> +	.nodes = { &qxm_dsp1 },
> +};
> +
> +static struct qcom_icc_bcm bcm_mc0 = {
> +	.name = "MC0",
> +	.keepalive = true,
> +	.num_nodes = 1,
> +	.nodes = { &ebi },
> +};
> +
> +static struct qcom_icc_bcm bcm_mm0 = {
> +	.name = "MM0",
> +	.keepalive = true,
> +	.num_nodes = 5,
> +	.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
> +		   &qnm_mdp0_1, &qnm_mdp1_0,
> +		   &qns_mem_noc_hf },
> +};
> +
> +static struct qcom_icc_bcm bcm_mm1 = {
> +	.name = "MM1",
> +	.num_nodes = 7,
> +	.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
> +		   &qnm_video0, &qnm_video1,
> +		   &qnm_video_cvp, &qnm_video_v_cpu,
> +		   &qns_mem_noc_sf },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsa0 = {
> +	.name = "NSA0",
> +	.num_nodes = 2,
> +	.nodes = { &qns_hcp, &qns_nsp_gemnoc },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsa1 = {
> +	.name = "NSA1",
> +	.num_nodes = 1,
> +	.nodes = { &qxm_nsp },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsb0 = {
> +	.name = "NSB0",
> +	.num_nodes = 2,
> +	.nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsb1 = {
> +	.name = "NSB1",
> +	.num_nodes = 1,
> +	.nodes = { &qxm_nspb },
> +};
> +
> +static struct qcom_icc_bcm bcm_pci0 = {
> +	.name = "PCI0",
> +	.num_nodes = 1,
> +	.nodes = { &qns_pcie_mem_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_qup0 = {
> +	.name = "QUP0",
> +	.vote_scale = 1,
> +	.num_nodes = 1,
> +	.nodes = { &qup0_core_slave },
> +};
> +
> +static struct qcom_icc_bcm bcm_qup1 = {
> +	.name = "QUP1",
> +	.vote_scale = 1,
> +	.num_nodes = 1,
> +	.nodes = { &qup1_core_slave },
> +};
> +
> +static struct qcom_icc_bcm bcm_qup2 = {
> +	.name = "QUP2",
> +	.vote_scale = 1,
> +	.num_nodes = 2,
> +	.nodes = { &qup2_core_slave, &qup3_core_slave },
> +};
> +
> +static struct qcom_icc_bcm bcm_sh0 = {
> +	.name = "SH0",
> +	.keepalive = true,
> +	.num_nodes = 1,
> +	.nodes = { &qns_llcc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sh2 = {
> +	.name = "SH2",
> +	.num_nodes = 1,
> +	.nodes = { &chm_apps },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn0 = {
> +	.name = "SN0",
> +	.keepalive = true,
> +	.num_nodes = 1,
> +	.nodes = { &qns_gemnoc_sf },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn1 = {
> +	.name = "SN1",
> +	.num_nodes = 1,
> +	.nodes = { &qns_gemnoc_gc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn2 = {
> +	.name = "SN2",
> +	.num_nodes = 1,
> +	.nodes = { &qxs_pimem },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn3 = {
> +	.name = "SN3",
> +	.num_nodes = 2,
> +	.nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn4 = {
> +	.name = "SN4",
> +	.num_nodes = 2,
> +	.nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn9 = {
> +	.name = "SN9",
> +	.num_nodes = 2,
> +	.nodes = { &qns_sysnoc, &qnm_lpass_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn10 = {
> +	.name = "SN10",
> +	.num_nodes = 1,
> +	.nodes = { &xs_qdss_stm },
> +};
> +
> +static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
> +	&bcm_sn3,
> +};
> +
> +static struct qcom_icc_node *aggre1_noc_nodes[] = {
> +	[MASTER_QUP_3] = &qxm_qup3,
> +	[MASTER_EMAC] = &xm_emac_0,
> +	[MASTER_EMAC_1] = &xm_emac_1,
> +	[MASTER_SDC] = &xm_sdc1,
> +	[MASTER_UFS_MEM] = &xm_ufs_mem,
> +	[MASTER_USB2] = &xm_usb2_2,
> +	[MASTER_USB3_0] = &xm_usb3_0,
> +	[MASTER_USB3_1] = &xm_usb3_1,
> +	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_aggre1_noc = {
> +	.nodes = aggre1_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
> +	.bcms = aggre1_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
> +	&bcm_ce0,
> +	&bcm_sn4,
> +};
> +
> +static struct qcom_icc_node *aggre2_noc_nodes[] = {
> +	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
> +	[MASTER_QUP_0] = &qhm_qup0,
> +	[MASTER_QUP_1] = &qhm_qup1,
> +	[MASTER_QUP_2] = &qhm_qup2,
> +	[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
> +	[MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
> +	[MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
> +	[MASTER_IPA] = &qxm_ipa,
> +	[MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
> +	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
> +	[MASTER_UFS_CARD] = &xm_ufs_card,
> +	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_aggre2_noc = {
> +	.nodes = aggre2_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
> +	.bcms = aggre2_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *clk_virt_bcms[] = {
> +	&bcm_qup0,
> +	&bcm_qup1,
> +	&bcm_qup2,
> +};
> +
> +static struct qcom_icc_node *clk_virt_nodes[] = {
> +	[MASTER_QUP_CORE_0] = &qup0_core_master,
> +	[MASTER_QUP_CORE_1] = &qup1_core_master,
> +	[MASTER_QUP_CORE_2] = &qup2_core_master,
> +	[MASTER_QUP_CORE_3] = &qup3_core_master,
> +	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
> +	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
> +	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
> +	[SLAVE_QUP_CORE_3] = &qup3_core_slave,
> +};
> +
> +static struct qcom_icc_desc sa8775p_clk_virt = {
> +	.nodes = clk_virt_nodes,
> +	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
> +	.bcms = clk_virt_bcms,
> +	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
> +};
> +
> +static struct qcom_icc_bcm *config_noc_bcms[] = {
> +	&bcm_cn0,
> +	&bcm_cn1,
> +	&bcm_cn2,
> +	&bcm_cn3,
> +	&bcm_sn2,
> +	&bcm_sn10,
> +};
> +
> +static struct qcom_icc_node *config_noc_nodes[] = {
> +	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
> +	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
> +	[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
> +	[SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
> +	[SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
> +	[SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
> +	[SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
> +	[SLAVE_AOSS] = &qhs_aoss,
> +	[SLAVE_APPSS] = &qhs_apss,
> +	[SLAVE_BOOT_ROM] = &qhs_boot_rom,
> +	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
> +	[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
> +	[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
> +	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
> +	[SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
> +	[SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
> +	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
> +	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
> +	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
> +	[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
> +	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
> +	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
> +	[SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
> +	[SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
> +	[SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
> +	[SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
> +	[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
> +	[SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
> +	[SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
> +	[SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
> +	[SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
> +	[SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
> +	[SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
> +	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
> +	[SLAVE_HWKM] = &qhs_hwkm,
> +	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
> +	[SLAVE_IPA_CFG] = &qhs_ipa,
> +	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
> +	[SLAVE_LPASS] = &qhs_lpass_cfg,
> +	[SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
> +	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
> +	[SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
> +	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
> +	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
> +	[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
> +	[SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
> +	[SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
> +	[SLAVE_PDM] = &qhs_pdm,
> +	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
> +	[SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
> +	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
> +	[SLAVE_QM_CFG] = &qhs_qm_cfg,
> +	[SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
> +	[SLAVE_QUP_0] = &qhs_qup0,
> +	[SLAVE_QUP_1] = &qhs_qup1,
> +	[SLAVE_QUP_2] = &qhs_qup2,
> +	[SLAVE_QUP_3] = &qhs_qup3,
> +	[SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
> +	[SLAVE_SDC1] = &qhs_sdc1,
> +	[SLAVE_SECURITY] = &qhs_security,
> +	[SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
> +	[SLAVE_TCSR] = &qhs_tcsr,
> +	[SLAVE_TLMM] = &qhs_tlmm,
> +	[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
> +	[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
> +	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
> +	[SLAVE_USB2] = &qhs_usb2_0,
> +	[SLAVE_USB3_0] = &qhs_usb3_0,
> +	[SLAVE_USB3_1] = &qhs_usb3_1,
> +	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
> +	[SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
> +	[SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
> +	[SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
> +	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
> +	[SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
> +	[SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
> +	[SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
> +	[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
> +	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
> +	[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
> +	[SLAVE_IMEM] = &qxs_imem,
> +	[SLAVE_PIMEM] = &qxs_pimem,
> +	[SLAVE_PCIE_0] = &xs_pcie_0,
> +	[SLAVE_PCIE_1] = &xs_pcie_1,
> +	[SLAVE_QDSS_STM] = &xs_qdss_stm,
> +	[SLAVE_TCU] = &xs_sys_tcu_cfg,
> +};
> +
> +static struct qcom_icc_desc sa8775p_config_noc = {
> +	.nodes = config_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(config_noc_nodes),
> +	.bcms = config_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(config_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *dc_noc_bcms[] = {
> +};
> +
> +static struct qcom_icc_node *dc_noc_nodes[] = {
> +	[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
> +	[SLAVE_LLCC_CFG] = &qhs_llcc,
> +	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_dc_noc = {
> +	.nodes = dc_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
> +	.bcms = dc_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *gem_noc_bcms[] = {
> +	&bcm_sh0,
> +	&bcm_sh2,
> +};
> +
> +static struct qcom_icc_node *gem_noc_nodes[] = {
> +	[MASTER_GPU_TCU] = &alm_gpu_tcu,
> +	[MASTER_PCIE_TCU] = &alm_pcie_tcu,
> +	[MASTER_SYS_TCU] = &alm_sys_tcu,
> +	[MASTER_APPSS_PROC] = &chm_apps,
> +	[MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
> +	[MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
> +	[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
> +	[MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
> +	[MASTER_GFX3D] = &qnm_gpu,
> +	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
> +	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
> +	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
> +	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
> +	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
> +	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
> +	[SLAVE_LLCC] = &qns_llcc,
> +	[SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
> +	[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
> +	[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
> +	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
> +	[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
> +};
> +
> +static struct qcom_icc_desc sa8775p_gem_noc = {
> +	.nodes = gem_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
> +	.bcms = gem_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
> +	&bcm_gna0,
> +	&bcm_gnb0,
> +};
> +
> +static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
> +	[MASTER_DSP0] = &qxm_dsp0,
> +	[MASTER_DSP1] = &qxm_dsp1,
> +	[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_gpdsp_anoc = {
> +	.nodes = gpdsp_anoc_nodes,
> +	.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
> +	.bcms = gpdsp_anoc_bcms,
> +	.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
> +	&bcm_sn9,
> +};
> +
> +static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
> +	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
> +	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
> +	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
> +	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
> +	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
> +	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
> +	[SLAVE_LPASS_SNOC] = &qns_sysnoc,
> +	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
> +	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_lpass_ag_noc = {
> +	.nodes = lpass_ag_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
> +	.bcms = lpass_ag_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *mc_virt_bcms[] = {
> +	&bcm_acv,
> +	&bcm_mc0,
> +};
> +
> +static struct qcom_icc_node *mc_virt_nodes[] = {
> +	[MASTER_LLCC] = &llcc_mc,
> +	[SLAVE_EBI1] = &ebi,
> +};
> +
> +static struct qcom_icc_desc sa8775p_mc_virt = {
> +	.nodes = mc_virt_nodes,
> +	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
> +	.bcms = mc_virt_bcms,
> +	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
> +};
> +
> +static struct qcom_icc_bcm *mmss_noc_bcms[] = {
> +	&bcm_mm0,
> +	&bcm_mm1,
> +};
> +
> +static struct qcom_icc_node *mmss_noc_nodes[] = {
> +	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
> +	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
> +	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
> +	[MASTER_MDP0] = &qnm_mdp0_0,
> +	[MASTER_MDP1] = &qnm_mdp0_1,
> +	[MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
> +	[MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
> +	[MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
> +	[MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
> +	[MASTER_VIDEO_P0] = &qnm_video0,
> +	[MASTER_VIDEO_P1] = &qnm_video1,
> +	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
> +	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
> +	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
> +	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
> +	[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
> +	[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
> +};
> +
> +static struct qcom_icc_desc sa8775p_mmss_noc = {
> +	.nodes = mmss_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
> +	.bcms = mmss_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *nspa_noc_bcms[] = {
> +	&bcm_nsa0,
> +	&bcm_nsa1,
> +};
> +
> +static struct qcom_icc_node *nspa_noc_nodes[] = {
> +	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
> +	[MASTER_CDSP_PROC] = &qxm_nsp,
> +	[SLAVE_HCP_A] = &qns_hcp,
> +	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
> +	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_nspa_noc = {
> +	.nodes = nspa_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
> +	.bcms = nspa_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *nspb_noc_bcms[] = {
> +	&bcm_nsb0,
> +	&bcm_nsb1,
> +};
> +
> +static struct qcom_icc_node *nspb_noc_nodes[] = {
> +	[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
> +	[MASTER_CDSP_PROC_B] = &qxm_nspb,
> +	[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
> +	[SLAVE_HCP_B] = &qns_nspb_hcp,
> +	[SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_nspb_noc = {
> +	.nodes = nspb_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
> +	.bcms = nspb_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
> +
> +};
> +
> +static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
> +	&bcm_pci0,
> +};
> +
> +static struct qcom_icc_node *pcie_anoc_nodes[] = {
> +	[MASTER_PCIE_0] = &xm_pcie3_0,
> +	[MASTER_PCIE_1] = &xm_pcie3_1,
> +	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_pcie_anoc = {
> +	.nodes = pcie_anoc_nodes,
> +	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
> +	.bcms = pcie_anoc_bcms,
> +	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *system_noc_bcms[] = {
> +	&bcm_sn0,
> +	&bcm_sn1,
> +	&bcm_sn3,
> +	&bcm_sn4,
> +	&bcm_sn9,
> +};
> +
> +static struct qcom_icc_node *system_noc_nodes[] = {
> +	[MASTER_GIC_AHB] = &qhm_gic,
> +	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
> +	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
> +	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
> +	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
> +	[MASTER_PIMEM] = &qxm_pimem,
> +	[MASTER_GIC] = &xm_gic,
> +	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
> +	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
> +	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_system_noc = {
> +	.nodes = system_noc_nodes,
> +	.num_nodes = ARRAY_SIZE(system_noc_nodes),
> +	.bcms = system_noc_bcms,
> +	.num_bcms = ARRAY_SIZE(system_noc_bcms),
> +};
> +
> +static const struct of_device_id qnoc_of_match[] = {
> +	{ .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
> +	{ .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
> +	{ .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
> +	{ .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
> +	{ .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
> +	{ .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
> +	{ .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
> +	{ .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
> +	{ .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
> +	{ .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
> +	{ .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
> +	{ .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
> +	{ .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
> +	{ .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, qnoc_of_match);
> +
> +static struct platform_driver qnoc_driver = {
> +	.probe = qcom_icc_rpmh_probe,
> +	.remove = qcom_icc_rpmh_remove,
> +	.driver = {
> +		.name = "qnoc-sa8775p",
> +		.of_match_table = qnoc_of_match,
> +		.sync_state = icc_sync_state,
> +	},
> +};
> +
> +static int __init qnoc_driver_init(void)
> +{
> +	return platform_driver_register(&qnoc_driver);
> +}
> +core_initcall(qnoc_driver_init);
> +
> +static void __exit qnoc_driver_exit(void)
> +{
> +	platform_driver_unregister(&qnoc_driver);
> +}
> +module_exit(qnoc_driver_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
> +MODULE_LICENSE("GPL");

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Enable the Qualcomm SA8775P interconnect driver for arm64 builds. It's
> required to be built-in for QUPv3 to work early which in turn is needed
> for the console.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 1cb586125c46..d5c938adbd2d 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1332,6 +1332,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8916=m
>  CONFIG_INTERCONNECT_QCOM_MSM8996=m
>  CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>  CONFIG_INTERCONNECT_QCOM_QCS404=m
> +CONFIG_INTERCONNECT_QCOM_SA8775P=y
>  CONFIG_INTERCONNECT_QCOM_SC7180=y
>  CONFIG_INTERCONNECT_QCOM_SC7280=y
>  CONFIG_INTERCONNECT_QCOM_SC8180X=y

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Yadu MG <quic_ymg@quicinc.com>
> 
> Add support for Lemans TLMM configuration and control via the pinctrl
> framework.
> 
> Signed-off-by: Yadu MG <quic_ymg@quicinc.com>
> Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com>
> [Bartosz: made the driver ready for upstream]
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---

[...]

> +
> +static const char * const gpio_groups[] = {
> +	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> +	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> +	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> +	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> +	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> +	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> +	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> +	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> +	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> +	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
> +	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
> +	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
> +	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
> +	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
> +	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
> +	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
> +	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
> +	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
> +	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
> +	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
> +	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
> +	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
> +	"gpio147", "gpio148",
> +};
> +static const char * const atest_char_groups[] = {
A newline after };-s would make this consistent with other drivers.

[...]

> +
> +/* Every pin is maintained as a single group, and missing or non-existing pin
/*
 * Every pin

With these nits:

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
> + * would be maintained as dummy group to synchronize pin group index with
> + * pin descriptor registered with pinctrl core.
> + * Clients would not be able to request these dummy pin groups.
> + */
> +static const struct msm_pingroup sa8775p_groups[] = {
> +	[0] = PINGROUP(0, _, _, _, _, _, _, _, _, _),
> +	[1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _),
> +	[2] = PINGROUP(2, _, _, _, _, _, _, _, _, _),
> +	[3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _),
> +	[4] = PINGROUP(4, _, _, _, _, _, _, _, _, _),
> +	[5] = PINGROUP(5, _, _, _, _, _, _, _, _, _),
> +	[6] = PINGROUP(6, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _, _),
> +	[7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _),
> +	[8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _),
> +	[9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _),
> +	[10] = PINGROUP(10, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _),
> +	[11] = PINGROUP(11, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _),
> +	[12] = PINGROUP(12, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp,
> +			emac0_mcg0, _, _, _),
> +	[13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _),
> +	[14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _),
> +	[15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _),
> +	[16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _),
> +	[17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _),
> +	[18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _),
> +	[19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _),
> +	[20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _),
> +	[21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _),
> +	[22] = PINGROUP(22, qup0_se0, qdss_gpio15, _, _, _, _, _, _, _),
> +	[23] = PINGROUP(23, qup0_se0, qdss_gpio14, _, _, _, _, _, _, _),
> +	[24] = PINGROUP(24, qup0_se1, qdss_gpio13, _, _, _, _, _, _, _),
> +	[25] = PINGROUP(25, qup0_se1, phase_flag31, _, qdss_gpio12, _, _, _, _, _),
> +	[26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag30, _, _, _, _, _),
> +	[27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag29, _, atest_char, _, _, _, _),
> +	[28] = PINGROUP(28, qup0_se3, phase_flag28, _, qdss_gpio11, _, _, _, _, _),
> +	[29] = PINGROUP(29, qup0_se3, phase_flag27, _, qdss_gpio10, _, _, _, _, _),
> +	[30] = PINGROUP(30, qup0_se3, phase_flag26, _, qdss_gpio9, _, _, _, _, _),
> +	[31] = PINGROUP(31, qup0_se3, phase_flag25, _, qdss_gpio8, _, _, _, _, _),
> +	[32] = PINGROUP(32, qup0_se4, phase_flag24, _, _, _, _, _, _, _),
> +	[33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _,	_),
> +	[34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _,	_),
> +	[35] = PINGROUP(35, qup0_se4, phase_flag23, _, _, _, _, _, _, _),
> +	[36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag22, tgu_ch2, _, _, _, _, _),
> +	[37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag21, tgu_ch3, _, _, _, _, _),
> +	[38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag20, tgu_ch4, _, _, _, _),
> +	[39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag19, tgu_ch5, _, _, _, _),
> +	[40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _),
> +	[41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _),
> +	[42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _),
> +	[43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _),
> +	[44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _),
> +	[45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _),
> +	[46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _),
> +	[47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _),
> +	[48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _),
> +	[49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _),
> +	[50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _),
> +	[51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _),
> +	[52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7,	gcc_gp2, _, ddr_pxi1, _, _),
> +	[53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _),
> +	[54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _),
> +	[55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _),
> +	[56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag18,
> +			ddr_bist, _, _, _),
> +	[57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0,
> +			phase_flag17, ddr_bist, _, _),
> +	[58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char1, _, _, _),
> +	[59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char0, _, _, _),
> +	[60] = PINGROUP(60, cci_i2c, qdss_gpio0, _, _, _, _, _, _, _),
> +	[61] = PINGROUP(61, cci_i2c, qdss_gpio1, _, _, _, _, _, _, _),
> +	[62] = PINGROUP(62, cci_i2c, qdss_gpio2, _, _, _, _, _, _, _),
> +	[63] = PINGROUP(63, cci_i2c, qdss_gpio3, _, _, _, _, _, _, _),
> +	[64] = PINGROUP(64, cci_i2c, qdss_gpio4, _, _, _, _, _, _, _),
> +	[65] = PINGROUP(65, cci_i2c, qdss_gpio5, _, _, _, _, _, _, _),
> +	[66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio6, _, _, _, _, _, _),
> +	[67] = PINGROUP(67, cci_i2c, qdss_gpio7, _, _, _, _, _, _, _),
> +	[68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _),
> +	[69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _),
> +	[70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _),
> +	[71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _),
> +	[72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _),
> +	[73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _),
> +	[74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _),
> +	[75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _),
> +	[76] = PINGROUP(76, _, _, _, _, _, _, _, _, _),
> +	[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
> +	[78] = PINGROUP(78, _, _, _, _, _, _, _, _, _),
> +	[79] = PINGROUP(79, _, _, _, _, _, _, _, _, _),
> +	[80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _),
> +	[81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _),
> +	[82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _),
> +	[83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _),
> +	[84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _),
> +	[85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _),
> +	[86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _),
> +	[87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb20, ddr_pxi3, _, _, _, _, _),
> +	[88] = PINGROUP(88, qup2_se2, _, atest_usb21, ddr_pxi3, _, _, _, _, _),
> +	[89] = PINGROUP(89, qup2_se2, _, atest_usb22, ddr_pxi4, atest_char3, _, _, _, _),
> +	[90] = PINGROUP(90, qup2_se2, _, atest_usb23, ddr_pxi4, atest_char2, _, _, _, _),
> +	[91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb20, _, _, _, _, _),
> +	[92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb21, _, _, _, _, _),
> +	[93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb22, _, _, _, _, _),
> +	[94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb23, _, _, _, _, _),
> +	[95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb20, _, _, _, _, _),
> +	[96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb21, _, _, _, _, _),
> +	[97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb22, _, _, _, _),
> +	[98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag16, cri_trng1, _, _, _, _, _),
> +	[99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag15, cri_trng, _, _, _, _, _),
> +	[100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _),
> +	[101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _),
> +	[102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _),
> +	[103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _),
> +	[104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _),
> +	[105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb23, _, _, _, _, _),
> +	[106] = PINGROUP(106, mi2s1_sck, phase_flag14, _, qdss_gpio8, _, _, _, _, _),
> +	[107] = PINGROUP(107, mi2s1_ws, phase_flag13, _, qdss_gpio9, _, _, _, _, _),
> +	[108] = PINGROUP(108, mi2s1_data0, phase_flag12, _, qdss_gpio10, _, _, _, _, _),
> +	[109] = PINGROUP(109, mi2s1_data1, phase_flag11, _, qdss_gpio11, _, _, _, _, _),
> +	[110] = PINGROUP(110, mi2s2_sck, phase_flag10, _, qdss_gpio12, _, _, _, _, _),
> +	[111] = PINGROUP(111, mi2s2_ws, phase_flag9, _, qdss_gpio13, vsense_trigger, _, _, _, _),
> +	[112] = PINGROUP(112, mi2s2_data0, phase_flag8, _, qdss_gpio14, _, _, _, _, _),
> +	[113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag7, _, qdss_gpio15, _, _, _, _),
> +	[114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag6, _, qdss_gpio, _, _, _, _),
> +	[115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio0, _, _, _, _, _, _),
> +	[116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio1, _, _, _, _, _, _),
> +	[117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio2, _, _, _, _, _),
> +	[118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio3, ddr_pxi5, _, _, _, _, _),
> +	[119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio4, ddr_pxi5, _, _, _, _, _),
> +	[120] = PINGROUP(120, hs1_mi2s, phase_flag5, _, qdss_gpio5, _, _, _, _, _),
> +	[121] = PINGROUP(121, hs1_mi2s, phase_flag4, _, qdss_gpio6, _, _, _, _, _),
> +	[122] = PINGROUP(122, hs2_mi2s, phase_flag3, _, qdss_gpio7, _, _, _, _, _),
> +	[123] = PINGROUP(123, hs2_mi2s, phase_flag2, _, _, _, _, _, _, _),
> +	[124] = PINGROUP(124, hs2_mi2s, phase_flag1, _, _, _, _, _, _, _),
> +	[125] = PINGROUP(125, hs2_mi2s, phase_flag0, _, _, _, _, _, _, _),
> +	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
> +	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _),
> +	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _),
> +	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
> +	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
> +	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
> +	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
> +	[133] = PINGROUP(133, _, _, _, _, _, _, _, _, _),
> +	[134] = PINGROUP(134, _, _, _, _, _, _, _, _, _),
> +	[135] = PINGROUP(135, _, _, _, _, _, _, _, _, _),
> +	[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _),
> +	[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _),
> +	[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _),
> +	[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
> +	[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _),
> +	[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
> +	[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
> +	[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
> +	[144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _),
> +	[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
> +	[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
> +	[147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
> +	[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
> +	[149] = UFS_RESET(ufs_reset, 0x1a2000),
> +	[150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0),
> +	[151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6),
> +	[152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3),
> +	[153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0),
> +};
> +
> +static const struct msm_pinctrl_soc_data sa8775p_pinctrl = {
> +	.pins = sa8775p_pins,
> +	.npins = ARRAY_SIZE(sa8775p_pins),
> +	.functions = sa8775p_functions,
> +	.nfunctions = ARRAY_SIZE(sa8775p_functions),
> +	.groups = sa8775p_groups,
> +	.ngroups = ARRAY_SIZE(sa8775p_groups),
> +	.ngpios = 150,
> +};
> +
> +static int sa8775p_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return msm_pinctrl_probe(pdev, &sa8775p_pinctrl);
> +}
> +
> +static const struct of_device_id sa8775p_pinctrl_of_match[] = {
> +	{ .compatible = "qcom,sa8775p-pinctrl", },
> +	{ },
> +};
> +
> +static struct platform_driver sa8775p_pinctrl_driver = {
> +	.driver = {
> +		.name = "sa8775p-pinctrl",
> +		.of_match_table = sa8775p_pinctrl_of_match,
> +	},
> +	.probe = sa8775p_pinctrl_probe,
> +	.remove = msm_pinctrl_remove,
> +};
> +
> +static int __init sa8775p_pinctrl_init(void)
> +{
> +	return platform_driver_register(&sa8775p_pinctrl_driver);
> +}
> +arch_initcall(sa8775p_pinctrl_init);
> +
> +static void __exit sa8775p_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&sa8775p_pinctrl_driver);
> +}
> +module_exit(sa8775p_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("QTI SA8775P pinctrl driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match);

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Enable the Qualcomm SA8775P TLMM pinctrl and GPIO driver. It needs to be
> built-in for UART to provide a console.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index d5c938adbd2d..6c752b9a4565 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -555,6 +555,7 @@ CONFIG_PINCTRL_QCM2290=y
>  CONFIG_PINCTRL_QCS404=y
>  CONFIG_PINCTRL_QDF2XXX=y
>  CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
> +CONFIG_PINCTRL_SA8775P=y
>  CONFIG_PINCTRL_SC7180=y
>  CONFIG_PINCTRL_SC7280=y
>  CONFIG_PINCTRL_SC8180X=y

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Add power domain description for sa8775p and a new compatible to match it.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/soc/qcom/rpmhpd.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
> index 4c2d2c296790..f20e2a49a669 100644
> --- a/drivers/soc/qcom/rpmhpd.c
> +++ b/drivers/soc/qcom/rpmhpd.c
> @@ -187,6 +187,16 @@ static struct rpmhpd nsp = {
>  	.res_name = "nsp.lvl",
>  };
>  
> +static struct rpmhpd nsp0 = {
> +	.pd = { .name = "nsp0", },
> +	.res_name = "nsp0.lvl",
> +};
> +
> +static struct rpmhpd nsp1 = {
> +	.pd = { .name = "nsp1", },
> +	.res_name = "nsp1.lvl",
> +};
> +
>  static struct rpmhpd qphy = {
>  	.pd = { .name = "qphy", },
>  	.res_name = "qphy.lvl",
> @@ -212,6 +222,29 @@ static const struct rpmhpd_desc sa8540p_desc = {
>  	.num_pds = ARRAY_SIZE(sa8540p_rpmhpds),
>  };
>  
> +/* SA8775P RPMH power domains */
> +static struct rpmhpd *sa8775p_rpmhpds[] = {
> +	[SA8775P_CX] = &cx,
> +	[SA8775P_CX_AO] = &cx_ao,
> +	[SA8775P_EBI] = &ebi,
> +	[SA8775P_GFX] = &gfx,
> +	[SA8775P_LCX] = &lcx,
> +	[SA8775P_LMX] = &lmx,
> +	[SA8775P_MMCX] = &mmcx,
> +	[SA8775P_MMCX_AO] = &mmcx_ao,
> +	[SA8775P_MXC] = &mxc,
> +	[SA8775P_MXC_AO] = &mxc_ao,
> +	[SA8775P_MX] = &mx,
> +	[SA8775P_MX_AO] = &mx_ao,
> +	[SA8775P_NSP0] = &nsp0,
> +	[SA8775P_NSP1] = &nsp1,
> +};
> +
> +static const struct rpmhpd_desc sa8775p_desc = {
> +	.rpmhpds = sa8775p_rpmhpds,
> +	.num_pds = ARRAY_SIZE(sa8775p_rpmhpds),
> +};
> +
>  /* SDM670 RPMH powerdomains */
>  static struct rpmhpd *sdm670_rpmhpds[] = {
>  	[SDM670_CX] = &cx_w_mx_parent,
> @@ -487,6 +520,7 @@ static const struct rpmhpd_desc sc8280xp_desc = {
>  static const struct of_device_id rpmhpd_match_table[] = {
>  	{ .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc },
>  	{ .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc },
> +	{ .compatible = "qcom,sa8775p-rpmhpd", .data = &sa8775p_desc },
>  	{ .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc },
>  	{ .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc },
>  	{ .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc },

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Extend the driver to support the sa8775p platform.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 91d404deb115..5e12742fcfd9 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
/*
 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
 * special handling and can not be covered by the qcom,smmu-500 entry.
 */
> @@ -500,6 +500,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
>  	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
>  	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
> +	{ .compatible = "qcom,sa8775p-smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },

Document the property in bindings and follow it by "qcom,smmu-500", "arm,mmu-500"
instead.

Konrad

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Enable the Qualcomm SA8775P TLMM pinctrl and GPIO driver. It needs to be
> built-in for UART to provide a console.

One defconfig patch for entire SA8775p patchset. There is no point to
enable piece by piece because anyway each defconfig will have to go via
qcom soc tree.

Best regards,
Krzysztof

On 9.01.2023 18:58, Konrad Dybcio wrote:
> 
> 
> On 9.01.2023 18:44, Bartosz Golaszewski wrote:
>> From: Shazad Hussain <quic_shazhuss@quicinc.com>
>>
>> Add support for the Global Clock Controller found in the QTI SA8775P
>> platforms.
>>
>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>> [Bartosz: made the driver ready for upstream]
>> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> ---
> [...]
> 
>> +
>> +static struct gdsc usb20_prim_gdsc = {
>> +	.gdscr = 0x1C004,
> Please use lowercase hex literals outside #defines.
> 
>> +	.pd = {
>> +		.name = "usb20_prim_gdsc",
>> +	},
>> +	.pwrsts = PWRSTS_OFF_ON,
>> +};
>> +
> [...]
> 
>> +
>> +static const struct regmap_config gcc_sa8775p_regmap_config = {
>> +	.reg_bits = 32,
>> +	.reg_stride = 4,
>> +	.val_bits = 32,
>> +	.max_register = 0x472cffc,
> This is faaaaar more than what your DT node specifies.
> 
> With these two fixed, LGTM:
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Konrad
>> +	.fast_io = true,
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_sa8775p_desc = {
>> +	.config = &gcc_sa8775p_regmap_config,
>> +	.clks = gcc_sa8775p_clocks,
>> +	.num_clks = ARRAY_SIZE(gcc_sa8775p_clocks),
>> +	.resets = gcc_sa8775p_resets,
>> +	.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
>> +	.gdscs = gcc_sa8775p_gdscs,
>> +	.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
>> +};
>> +
>> +static const struct of_device_id gcc_sa8775p_match_table[] = {
>> +	{ .compatible = "qcom,gcc-sa8775p" },
One more thing, this should be qcom,sa8775p-gcc.

Konrad
>> +	{ }
>> +};
>> +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table);
>> +
>> +static int gcc_sa8775p_probe(struct platform_device *pdev)
>> +{
>> +	struct regmap *regmap;
>> +	int ret;
>> +
>> +	regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc);
>> +	if (IS_ERR(regmap))
>> +		return PTR_ERR(regmap);
>> +
>> +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>> +				       ARRAY_SIZE(gcc_dfs_clocks));
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * Keep the clocks always-ON
>> +	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK,
>> +	 * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
>> +	 * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK.
>> +	 */
>> +	regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0));
>> +	regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0));
>> +
>> +	return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
>> +}
>> +
>> +static struct platform_driver gcc_sa8775p_driver = {
>> +	.probe = gcc_sa8775p_probe,
>> +	.driver = {
>> +		.name = "gcc-sa8775p",
>> +		.of_match_table = gcc_sa8775p_match_table,
>> +	},
>> +};
>> +
>> +static int __init gcc_sa8775p_init(void)
>> +{
>> +	return platform_driver_register(&gcc_sa8775p_driver);
>> +}
>> +subsys_initcall(gcc_sa8775p_init);
>> +
>> +static void __exit gcc_sa8775p_exit(void)
>> +{
>> +	platform_driver_unregister(&gcc_sa8775p_driver);
>> +}
>> +module_exit(gcc_sa8775p_exit);
>> +
>> +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver");
>> +MODULE_LICENSE("GPL");

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Shazad Hussain <quic_shazhuss@quicinc.com>
> 
> Introduce QTI SA8775P-specific interconnect driver.
> 

> +
> +static struct qcom_icc_desc sa8775p_pcie_anoc = {
> +	.nodes = pcie_anoc_nodes,
> +	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
> +	.bcms = pcie_anoc_bcms,
> +	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *system_noc_bcms[] = {
> +	&bcm_sn0,
> +	&bcm_sn1,
> +	&bcm_sn3,
> +	&bcm_sn4,
> +	&bcm_sn9,
> +};
> +
> +static struct qcom_icc_node *system_noc_nodes[] = {
> +	[MASTER_GIC_AHB] = &qhm_gic,
> +	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
> +	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
> +	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
> +	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
> +	[MASTER_PIMEM] = &qxm_pimem,
> +	[MASTER_GIC] = &xm_gic,
> +	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
> +	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
> +	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_system_noc = {

This and several others are const, which means you started entire work
on some old code. It's quite a waste of your effort as now you have to
get all the patches we did for cleanups. Much better to start off from a
newest file. If you based work on downstream code, then this definitely
needs many fixes...

Best regards,
Krzysztof

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> This adds basic support for the Qualcomm sa8775p platform and the
> reference board: sa8775p-ride. The dt files describe the basics of the
> SoC and enable booting to shell.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/Makefile         |   1 +
>  arch/arm64/boot/dts/qcom/sa8775p-ride.dts |  39 +
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 841 ++++++++++++++++++++++
>  3 files changed, 881 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..39b8206f7131 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5-vision-mezzanine.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sa8155p-adp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sa8295p-adp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sa8540p-ride.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1-lte.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> new file mode 100644
> index 000000000000..d4dae32a84cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0-only
BSD3?

> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +
> +/ {
> +	model = "Qualcomm SA8875P Ride";
> +	compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
> +
> +	aliases {
> +		serial0 = &uart10;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&qupv3_id_1 {
> +	status = "okay";
> +};
> +
> +&uart10 {
> +	compatible = "qcom,geni-debug-uart";
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&qup_uart10_state>;
> +};
> +
> +&tlmm {
> +	qup_uart10_state: qup_uart10_state {
the node names (between ':' and '{') should end in -state,
but the label does not have to. In fact, you'll probably want
to have a "default" and a "sleep" state with different drive-strength
and bias properties.

> +		pins = "gpio46", "gpio47";
> +		function = "qup1_se3";
> +	};
> +};
Missing xo rate override.

> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> new file mode 100644
> index 000000000000..1a3b11628e38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -0,0 +1,841 @@
> +// SPDX-License-Identifier: GPL-2.0-only
BSD3?

> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sa8775p.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <32764>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +			L2_0: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +				L3_0: l3-cache {
> +				      compatible = "cache";
> +				};
> +			};
> +		};
> +
> +		CPU1: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x100>;
> +			enable-method = "psci";
> +			cpu-release-addr = <0x0 0x90000000>;
> +			next-level-cache = <&L2_1>;
> +			L2_1: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +			};
> +		};
> +
> +		CPU2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x200>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_2>;
> +			L2_2: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +			};
> +		};
> +
> +		CPU3: cpu@300 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x300>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_3>;
> +			L2_3: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +			};
> +		};
> +
> +		CPU4: cpu@10000 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10000>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_4>;
> +			L2_4: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +				L3_1: l3-cache {
> +				      compatible = "cache";
> +				};
> +
> +			};
> +		};
> +
> +		CPU5: cpu@10100 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10100>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_5>;
> +			L2_5: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +			};
> +		};
> +
> +		CPU6: cpu@10200 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10200>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_6>;
> +			L2_6: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +			};
> +		};
> +
> +		CPU7: cpu@10300 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10300>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_7>;
> +			L2_7: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +			};
> +		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&CPU0>;
> +				};
> +
> +				core1 {
> +					cpu = <&CPU1>;
> +				};
> +
> +				core2 {
> +					cpu = <&CPU2>;
> +				};
> +
> +				core3 {
> +					cpu = <&CPU3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&CPU4>;
> +				};
> +
> +				core1 {
> +					cpu = <&CPU5>;
> +				};
> +
> +				core2 {
> +					cpu = <&CPU6>;
> +				};
> +
> +				core3 {
> +					cpu = <&CPU7>;
> +				};
> +			};
> +		};
On other SoCs we define a single DynamIQ cluster, is it something
we should change?
> +	};
> +
> +	/* Will be updated by the bootloader. */
> +	memory {
The memory node should have a unit address, probably 0x80000000 in
your case, but please doublecheck (for example by reading the value
from /sys/firmware/)
> +		device_type = "memory";
> +		reg = <0 0 0 0>;
0x0 please

> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		sail_ss_mem: sail_ss_region@80000000 {
No underscores in node names, use -s instead.

> +			no-map;
> +			reg = <0x0 0x80000000 0x0 0x10000000>;
Please put reg above no-map.

> +		};
> +
> +		hyp_mem: hyp_region@90000000 {
> +			no-map;
> +			reg = <0x0 0x90000000 0x0 0x600000>;
> +		};
> +
> +		xbl_boot_mem: xbl_boot_region@90600000 {
> +			no-map;
> +			reg = <0x0 0x90600000 0x0 0x200000>;
> +		};
> +
> +		aop_image_mem: aop_image_region@90800000 {
> +			no-map;
> +			reg = <0x0 0x90800000 0x0 0x60000>;
> +		};
> +
> +		aop_cmd_db_mem: aop_cmd_db_region@90860000 {
> +			compatible = "qcom,cmd-db";
> +			no-map;
> +			reg = <0x0 0x90860000 0x0 0x20000>;
> +		};
> +
> +		uefi_log: uefi_log_region@908b0000 {
> +			no-map;
> +			reg = <0x0 0x908b0000 0x0 0x10000>;
> +		};
> +
> +		reserved_mem: reserved_region@908f0000 {
> +			no-map;
> +			reg = <0x0 0x908f0000 0x0 0xf000>;
> +		};
> +
> +		secdata_apss_mem: secdata_apss_region@908ff000 {
> +			no-map;
> +			reg = <0x0 0x908ff000 0x0 0x1000>;
> +		};
> +
> +		smem_mem: smem_region@90900000 {
> +			compatible = "qcom,smem";
> +			reg = <0x0 0x90900000 0x0 0x200000>;
> +			no-map;
> +			hwlocks = <&tcsr_mutex 3>;
> +		};
> +
> +		cpucp_fw_mem: cpucp_fw_region@90b00000 {
> +			no-map;
> +			reg = <0x0 0x90b00000 0x0 0x100000>;
> +		};
> +
> +		lpass_machine_learning_mem: lpass_machine_learning_region@93b00000 {
> +			no-map;
> +			reg = <0x0 0x93b00000 0x0 0xf00000>;
> +		};
> +
> +		adsp_rpc_remote_heap_mem: adsp_rpc_remote_heap_region@94a00000 {
> +			no-map;
> +			reg = <0x0 0x94a00000 0x0 0x800000>;
> +		};
> +
> +		pil_camera_mem: pil_camera_region@95200000 {
> +			no-map;
> +			reg = <0x0 0x95200000 0x0 0x500000>;
> +		};
> +
> +		pil_adsp_mem: pil_adsp_region@95c00000 {
> +			no-map;
> +			reg = <0x0 0x95c00000 0x0 0x1e00000>;
> +		};
> +
> +		pil_gdsp0_mem: pil_gdsp0_region@97b00000 {
> +			no-map;
> +			reg = <0x0 0x97b00000 0x0 0x1e00000>;
> +		};
> +
> +		pil_gdsp1_mem: pil_gdsp1_region@99900000 {
> +			no-map;
> +			reg = <0x0 0x99900000 0x0 0x1e00000>;
> +		};
> +
> +		pil_cdsp0_mem: pil_cdsp0_region@9b800000 {
> +			no-map;
> +			reg = <0x0 0x9b800000 0x0 0x1e00000>;
> +		};
> +
> +		pil_gpu_mem: pil_gpu_region@9d600000 {
> +			no-map;
> +			reg = <0x0 0x9d600000 0x0 0x2000>;
> +		};
> +
> +		pil_cdsp1_mem: pil_cdsp1_region@9d700000 {
> +			no-map;
> +			reg = <0x0 0x9d700000 0x0 0x1e00000>;
> +		};
> +
> +		pil_cvp_mem: pil_cvp_region@9f500000 {
> +			no-map;
> +			reg = <0x0 0x9f500000 0x0 0x700000>;
> +		};
> +
> +		pil_video_mem: pil_video_region@9fc00000 {
> +			no-map;
> +			reg = <0x0 0x9fc00000 0x0 0x700000>;
> +		};
> +
> +		hyptz_reserved_mem: hyptz_reserved_region@beb00000 {
> +			no-map;
> +			reg = <0x0 0xbeb00000 0x0 0x11500000>;
> +		};
> +
> +		tz_stat_mem: tz_stat_region@d0000000 {
> +			no-map;
> +			reg = <0x0 0xd0000000 0x0 0x100000>;
> +		};
> +
> +		tags_mem: tags_region@d0100000 {
> +			no-map;
> +			reg = <0x0 0xd0100000 0x0 0x1200000>;
> +		};
> +
> +		qtee_mem: qtee_region@d1300000 {
> +			no-map;
> +			reg = <0x0 0xd1300000 0x0 0x500000>;
> +		};
> +
> +		trusted_apps_mem: trusted_apps_region@d1800000 {
> +			no-map;
> +			reg = <0x0 0xd1800000 0x0 0x3900000>;
> +		};
> +
> +		dump_mem: mem_dump_region {
> +			compatible = "shared-dma-pool";
> +			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
> +			reusable;
> +			size = <0 0x3000000>;
> +		};
> +
> +		/* global autoconfigured region for contiguous allocations */
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
> +			reusable;
> +			alignment = <0x0 0x400000>;
> +			size = <0x0 0x2000000>;
> +			linux,cma-default;
> +		};
Are you sure these last two are useful?

> +	};
> +
> +	psci {
Top-level nodes should be sorted alphabetically.

> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	firmware {
> +		scm {
> +			compatible = "qcom,scm";
This one should also have a SoC-specific compatible.

> +		};
> +	};
> +
> +	qup_opp_table_100mhz: qup-100mhz-opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-100000000 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			required-opps = <&rpmhpd_opp_svs_l1>;
> +		};
> +	};
> +
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
You probably want 36 or more bits of addressing here, otherwise
SMMU translation will be playing jokes on you, cutting off some
bits..

> +
> +		gcc: clock-controller@100000 {
> +			compatible = "qcom,gcc-sa8775p";
Please update the compatible after you update it in the .c driver.

> +			reg = <0x100000 0xc7018>;
The GCC size is usually something more rounded to 0x1000, can you
doublecheck?

> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&sleep_clk>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>, /* TODO: usb_0_ssphy */
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>;
> +			power-domains = <&rpmhpd SA8775P_CX>;

compatible
reg
clocks
#clock-cells
#reset-cells
power-domains
#power-domain-cells

please
> +		};
> +
> +		ipcc: mailbox@408000 {
> +			compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
> +			reg = <0x408000 0x1000>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#mbox-cells = <2>;
> +		};
> +
> +		aggre1_noc:interconnect-aggre1-noc {
> +			compatible = "qcom,sa8775p-aggre1-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre2_noc: interconnect-aggre2-noc {
> +			compatible = "qcom,sa8775p-aggre2-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		clk_virt: interconnect-clk-virt {
> +			compatible = "qcom,sa8775p-clk-virt";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		config_noc: interconnect-config-noc {
> +			compatible = "qcom,sa8775p-config-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		dc_noc: interconnect-dc-noc {
> +			compatible = "qcom,sa8775p-dc-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		gem_noc: interconnect-gem-noc {
> +			compatible = "qcom,sa8775p-gem-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		gpdsp_anoc: interconnect-gpdsp-anoc {
> +			compatible = "qcom,sa8775p-gpdsp-anoc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		lpass_ag_noc: interconnect-lpass-ag-noc {
> +			compatible = "qcom,sa8775p-lpass-ag-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mc_virt: interconnect-mc-virt {
> +			compatible = "qcom,sa8775p-mc-virt";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mmss_noc: interconnect-mmss-noc {
> +			compatible = "qcom,sa8775p-mmss-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		nspa_noc: interconnect-nspa-noc {
> +			compatible = "qcom,sa8775p-nspa-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		nspb_noc: interconnect-nspb-noc {
> +			compatible = "qcom,sa8775p-nspb-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		pcie_anoc: interconnect-pcie-anoc {
> +			compatible = "qcom,sa8775p-pcie-anoc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		system_noc: interconnect-system-noc {
> +			compatible = "qcom,sa8775p-system-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		intc: interrupt-controller@17a00000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			#redistributor-regions = <1>;
> +			redistributor-stride = <0x0 0x20000>;
> +			reg = <0x17a00000 0x10000>,     /* GICD */
> +			      <0x17a60000 0x100000>;    /* GICR * 8 */
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
compatible
reg
interrupts
interrupt-controller
#interrupt-cells
redistributor-stride
#redistributor-regions

#address-cells
#size-cells
ranges;

please
> +		};
> +
> +		apps_rsc: rsc@18200000 {
> +			compatible = "qcom,rpmh-rsc";
> +			reg = <0x18200000 0x10000>,
> +			      <0x18210000 0x10000>,
> +			      <0x18220000 0x10000>;
> +			reg-names = "drv-0", "drv-1", "drv-2";
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +			      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Wrong indentation

> +			qcom,tcs-offset = <0xd00>;
> +			qcom,drv-id = <2>;
> +			qcom,tcs-config = <ACTIVE_TCS 2>,
> +					  <SLEEP_TCS 3>,
> +					  <WAKE_TCS 3>,
> +					  <CONTROL_TCS 0>;
> +			label = "apps_rsc";
Is it used anywhere?

> +
> +			apps_bcm_voter: bcm_voter {
> +				compatible = "qcom,bcm-voter";
> +			};
> +
> +			rpmhcc: clock-controller {
> +				compatible = "qcom,sa8775p-rpmh-clk";
> +				#clock-cells = <1>;
> +				clock-names = "xo";
> +				clocks = <&xo_board_clk>;
clocks
clock-names
#clock-cells
please

> +			};
> +
> +			rpmhpd: power-controller {
> +				compatible = "qcom,sa8775p-rpmhpd";
> +				#power-domain-cells = <1>;
> +				operating-points-v2 = <&rpmhpd_opp_table>;
operating-points-v2
#power-domain-cells
please
> +
> +				rpmhpd_opp_table: opp-table {
> +					compatible = "operating-points-v2";
> +
> +					rpmhpd_opp_ret: opp1 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> +					};
> +
> +					rpmhpd_opp_min_svs: opp2 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +					};
> +
> +					rpmhpd_opp_low_svs: opp3 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					};
> +
> +					rpmhpd_opp_svs: opp4 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					};
> +
> +					rpmhpd_opp_svs_l1: opp5 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					};
> +
> +					rpmhpd_opp_nom: opp6 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					};
> +
> +					rpmhpd_opp_nom_l1: opp7 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					};
> +
> +					rpmhpd_opp_nom_l2: opp8 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> +					};
> +
> +					rpmhpd_opp_turbo: opp9 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					};
> +
> +					rpmhpd_opp_turbo_l1: opp10 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					};
> +				};
> +			};
> +		};
> +
> +		arch_timer: timer {
Unnecessary label

> +			compatible = "arm,armv8-timer";
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +				     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
Shouldn't the last one be 10?

> +			clock-frequency = <19200000>;
Please remove this property, the 100 levels of firmware that boot before
Linux already program this.

> +		};
> +
> +		memtimer: timer@17c20000 {
Unnecessary label

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0x17c20000 0x1000>;
> +			clock-frequency = <19200000>;
Ditto


+ please sort to:
compatible
reg
#addr
#size
ranges
> +
> +			frame@17c21000 {
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c21000 0x1000>,
> +				      <0x17c22000 0x1000>;
reg
interrupts
frame-number
[status]

please
> +			};
> +
> +			frame@17c23000 {
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c23000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c25000 {
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c25000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c27000 {
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c27000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c29000 {
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c29000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c2b000 {
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c2b000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c2d000 {
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c2d000 0x1000>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		tcsr_mutex: hwlock@1f40000 {
> +			compatible = "qcom,tcsr-mutex";
> +			reg = <0x1f40000 0x20000>;
> +			#hwlock-cells = <1>;
> +		};
> +
> +		tlmm: pinctrl@f000000 {
> +			compatible = "qcom,sa8775p-pinctrl";
> +			reg = <0xf000000 0x1000000>;
All address fields under /soc should be padded to 8 hex digits and
nodes should be sorted by their unit address.

> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 149>;
> +		};
> +
> +		qcom-wdt@17c10000 {
> +			compatible = "qcom,kpss-wdt";
> +			reg = <0x17c10000 0x1000>;
> +			clocks = <&sleep_clk>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
Please reorder interrupts and clocks.

> +		};
> +
> +		qupv3_id_1: geniqup@ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0xac0000 0x6000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x443 0x0>;
> +			status = "disabled";
> +
> +			uart10: serial@a8c000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0xa8c000 0x4000>;
> +				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> +						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> +				power-domains = <&rpmhpd SA8775P_CX>;
> +				operating-points-v2 = <&qup_opp_table_100mhz>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		apps_smmu: apps-smmu@15000000 {
> +			compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500";
> +			reg = <0x15000000 0x100000>, <0x15182000 0x28>;
Only one reg is used (unless you're nvidia)...

> +			reg-names = "base", "tcu-base";
..and this becomes irrelevant.

> +			#iommu-cells = <2>;

> +			qcom,skip-init;
> +			qcom,use-3-lvl-tables;
These two don't exist upstream.
> +			#global-interrupts = <2>;

> +			#size-cells = <1>;
> +			#address-cells = <1>;
> +			ranges;
There are no child nodes of SMMU, please remove.
> +
> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
Bad indentation (or my mail client is drunk again)

Konrad
> +				      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
> +				      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};
> +};

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> This adds basic support for the Qualcomm sa8775p platform and the
> reference board: sa8775p-ride. The dt files describe the basics of the
> SoC and enable booting to shell.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/Makefile         |   1 +
>  arch/arm64/boot/dts/qcom/sa8775p-ride.dts |  39 +
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 841 ++++++++++++++++++++++
>  3 files changed, 881 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..39b8206f7131 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5-vision-mezzanine.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sa8155p-adp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sa8295p-adp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sa8540p-ride.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1-lte.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> new file mode 100644
> index 000000000000..d4dae32a84cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +
> +/ {
> +	model = "Qualcomm SA8875P Ride";
> +	compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
> +
> +	aliases {
> +		serial0 = &uart10;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&qupv3_id_1 {
> +	status = "okay";
> +};
> +
> +&uart10 {
> +	compatible = "qcom,geni-debug-uart";
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&qup_uart10_state>;
> +};
> +
> +&tlmm {
> +	qup_uart10_state: qup_uart10_state {

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> +		pins = "gpio46", "gpio47";
> +		function = "qup1_se3";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> new file mode 100644
> index 000000000000..1a3b11628e38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -0,0 +1,841 @@
> +// SPDX-License-Identifier: GPL-2.0-only

Why GPL-2.0-only? Isn't this based on other code which is either
dual-licensed or BSD license?

> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sa8775p.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;

Your board needs clock frequency.

> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <32764>;

Usual comment: this (entire clock or at least its frequency) is usually
not a property of a SoC, but board. Did something change here in SA8775?


> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +			L2_0: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;

Messed indentation.

> +				L3_0: l3-cache {
> +				      compatible = "cache";
> +				};
> +			};
> +		};
> +
> +		CPU1: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x100>;
> +			enable-method = "psci";
> +			cpu-release-addr = <0x0 0x90000000>;
> +			next-level-cache = <&L2_1>;
> +			L2_1: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +			};
> +		};
> +
> +		CPU2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x200>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_2>;
> +			L2_2: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +			};
> +		};
> +
> +		CPU3: cpu@300 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x300>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_3>;
> +			L2_3: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_0>;
> +			};
> +		};
> +
> +		CPU4: cpu@10000 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10000>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_4>;
> +			L2_4: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +				L3_1: l3-cache {
> +				      compatible = "cache";
> +				};
> +
> +			};
> +		};
> +
> +		CPU5: cpu@10100 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10100>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_5>;
> +			L2_5: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +			};
> +		};
> +
> +		CPU6: cpu@10200 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10200>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_6>;
> +			L2_6: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +			};
> +		};
> +
> +		CPU7: cpu@10300 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo";
> +			reg = <0x0 0x10300>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_7>;
> +			L2_7: l2-cache {
> +			      compatible = "cache";
> +			      next-level-cache = <&L3_1>;
> +			};
> +		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&CPU0>;
> +				};
> +
> +				core1 {
> +					cpu = <&CPU1>;
> +				};
> +
> +				core2 {
> +					cpu = <&CPU2>;
> +				};
> +
> +				core3 {
> +					cpu = <&CPU3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&CPU4>;
> +				};
> +
> +				core1 {
> +					cpu = <&CPU5>;
> +				};
> +
> +				core2 {
> +					cpu = <&CPU6>;
> +				};
> +
> +				core3 {
> +					cpu = <&CPU7>;
> +				};
> +			};
> +		};
> +	};
> +
> +	/* Will be updated by the bootloader. */
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0 0 0>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		sail_ss_mem: sail_ss_region@80000000 {

No underscores in node names.

(...)

> +
> +	qup_opp_table_100mhz: qup-100mhz-opp-table {

opp-table-....

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> +		compatible = "operating-points-v2";
> +
> +		opp-100000000 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			required-opps = <&rpmhpd_opp_svs_l1>;
> +		};
> +	};
> +
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
> +
> +		gcc: clock-controller@100000 {
> +			compatible = "qcom,gcc-sa8775p";
> +			reg = <0x100000 0xc7018>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&sleep_clk>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>, /* TODO: usb_0_ssphy */
> +				 <0>,
> +				 <0>,
> +				 <0>,
> +				 <0>;
> +			power-domains = <&rpmhpd SA8775P_CX>;
> +		};
> +
> +		ipcc: mailbox@408000 {
> +			compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
> +			reg = <0x408000 0x1000>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#mbox-cells = <2>;
> +		};
> +
> +		aggre1_noc:interconnect-aggre1-noc {

Missing space after :

> +			compatible = "qcom,sa8775p-aggre1-noc";

This does not match your bindings, so nothing here was tested against
your own files which you sent.

> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre2_noc: interconnect-aggre2-noc {
> +			compatible = "qcom,sa8775p-aggre2-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		clk_virt: interconnect-clk-virt {
> +			compatible = "qcom,sa8775p-clk-virt";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		config_noc: interconnect-config-noc {
> +			compatible = "qcom,sa8775p-config-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		dc_noc: interconnect-dc-noc {
> +			compatible = "qcom,sa8775p-dc-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		gem_noc: interconnect-gem-noc {
> +			compatible = "qcom,sa8775p-gem-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		gpdsp_anoc: interconnect-gpdsp-anoc {
> +			compatible = "qcom,sa8775p-gpdsp-anoc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		lpass_ag_noc: interconnect-lpass-ag-noc {
> +			compatible = "qcom,sa8775p-lpass-ag-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mc_virt: interconnect-mc-virt {
> +			compatible = "qcom,sa8775p-mc-virt";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mmss_noc: interconnect-mmss-noc {
> +			compatible = "qcom,sa8775p-mmss-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		nspa_noc: interconnect-nspa-noc {
> +			compatible = "qcom,sa8775p-nspa-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		nspb_noc: interconnect-nspb-noc {
> +			compatible = "qcom,sa8775p-nspb-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		pcie_anoc: interconnect-pcie-anoc {
> +			compatible = "qcom,sa8775p-pcie-anoc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		system_noc: interconnect-system-noc {
> +			compatible = "qcom,sa8775p-system-noc";
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		intc: interrupt-controller@17a00000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			#redistributor-regions = <1>;
> +			redistributor-stride = <0x0 0x20000>;
> +			reg = <0x17a00000 0x10000>,     /* GICD */
> +			      <0x17a60000 0x100000>;    /* GICR * 8 */

Compatible goes first, then reg, then ranges.

> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		apps_rsc: rsc@18200000 {
> +			compatible = "qcom,rpmh-rsc";
> +			reg = <0x18200000 0x10000>,
> +			      <0x18210000 0x10000>,
> +			      <0x18220000 0x10000>;
> +			reg-names = "drv-0", "drv-1", "drv-2";
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +			      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +			qcom,tcs-offset = <0xd00>;
> +			qcom,drv-id = <2>;
> +			qcom,tcs-config = <ACTIVE_TCS 2>,
> +					  <SLEEP_TCS 3>,
> +					  <WAKE_TCS 3>,
> +					  <CONTROL_TCS 0>;
> +			label = "apps_rsc";
> +
> +			apps_bcm_voter: bcm_voter {

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> +				compatible = "qcom,bcm-voter";
> +			};
> +
> +			rpmhcc: clock-controller {
> +				compatible = "qcom,sa8775p-rpmh-clk";
> +				#clock-cells = <1>;
> +				clock-names = "xo";
> +				clocks = <&xo_board_clk>;
> +			};
> +
> +			rpmhpd: power-controller {
> +				compatible = "qcom,sa8775p-rpmhpd";
> +				#power-domain-cells = <1>;
> +				operating-points-v2 = <&rpmhpd_opp_table>;
> +
> +				rpmhpd_opp_table: opp-table {
> +					compatible = "operating-points-v2";
> +
> +					rpmhpd_opp_ret: opp1 {

opp-0
(so numbering from 0 and hyphen)

> +						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> +					};
> +
> +					rpmhpd_opp_min_svs: opp2 {

opp-1

> +						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +					};
> +
> +					rpmhpd_opp_low_svs: opp3 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					};
> +
> +					rpmhpd_opp_svs: opp4 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					};
> +
> +					rpmhpd_opp_svs_l1: opp5 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					};
> +
> +					rpmhpd_opp_nom: opp6 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					};
> +
> +					rpmhpd_opp_nom_l1: opp7 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					};
> +
> +					rpmhpd_opp_nom_l2: opp8 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> +					};
> +
> +					rpmhpd_opp_turbo: opp9 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					};
> +
> +					rpmhpd_opp_turbo_l1: opp10 {
> +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					};
> +				};
> +			};
> +		};
> +
> +		arch_timer: timer {
> +			compatible = "arm,armv8-timer";
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +				     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> +			clock-frequency = <19200000>;
> +		};
> +
> +		memtimer: timer@17c20000 {

Why this one is outside of soc node? Or are we inside soc? But then
ARMv8 timer cannot be here... dtbs W=1 would warn you, wouldn't it?


> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			compatible = "arm,armv7-timer-mem";

Weird order of properties.

> +			reg = <0x17c20000 0x1000>;
> +			clock-frequency = <19200000>;
> +
> +			frame@17c21000 {
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c21000 0x1000>,
> +				      <0x17c22000 0x1000>;
> +			};
> +
> +			frame@17c23000 {
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c23000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c25000 {
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c25000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c27000 {
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c27000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c29000 {
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c29000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c2b000 {
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c2b000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17c2d000 {
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17c2d000 0x1000>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		tcsr_mutex: hwlock@1f40000 {
> +			compatible = "qcom,tcsr-mutex";
> +			reg = <0x1f40000 0x20000>;
> +			#hwlock-cells = <1>;
> +		};
> +
> +		tlmm: pinctrl@f000000 {
> +			compatible = "qcom,sa8775p-pinctrl";
> +			reg = <0xf000000 0x1000000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 149>;
> +		};
> +
> +		qcom-wdt@17c10000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> +			compatible = "qcom,kpss-wdt";
> +			reg = <0x17c10000 0x1000>;
> +			clocks = <&sleep_clk>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		qupv3_id_1: geniqup@ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0xac0000 0x6000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x443 0x0>;
> +			status = "disabled";
> +
> +			uart10: serial@a8c000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0xa8c000 0x4000>;
> +				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> +						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> +				power-domains = <&rpmhpd SA8775P_CX>;
> +				operating-points-v2 = <&qup_opp_table_100mhz>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		apps_smmu: apps-smmu@15000000 {

iommu, node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

and probably also fails dtbs_check...

> +			compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500";
> +			reg = <0x15000000 0x100000>, <0x15182000 0x28>;
> +			reg-names = "base", "tcu-base";
> +			#iommu-cells = <2>;
> +			qcom,skip-init;
> +			qcom,use-3-lvl-tables;
> +			#global-interrupts = <2>;
> +			#size-cells = <1>;

Best regards,
Krzysztof

On 09/01/2023 19:10, Konrad Dybcio wrote:
> 
> 
> On 9.01.2023 18:45, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>
>> Extend the driver to support the sa8775p platform.
>>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> ---
>>  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> index 91d404deb115..5e12742fcfd9 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> /*
>  * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
>  * special handling and can not be covered by the qcom,smmu-500 entry.
>  */

We should change the default -U argument for git format-patch :)

Best regards,
Krzysztof

On 09/01/2023 19:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Add power domain description for sa8775p and a new compatible to match it.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>   drivers/soc/qcom/rpmhpd.c | 34 ++++++++++++++++++++++++++++++++++
>   1 file changed, 34 insertions(+)

[skipped]

> +/* SA8775P RPMH power domains */
> +static struct rpmhpd *sa8775p_rpmhpds[] = {
> +	[SA8775P_CX] = &cx,
> +	[SA8775P_CX_AO] = &cx_ao,
> +	[SA8775P_EBI] = &ebi,
> +	[SA8775P_GFX] = &gfx,
> +	[SA8775P_LCX] = &lcx,
> +	[SA8775P_LMX] = &lmx,
> +	[SA8775P_MMCX] = &mmcx,
> +	[SA8775P_MMCX_AO] = &mmcx_ao,
> +	[SA8775P_MXC] = &mxc,
> +	[SA8775P_MXC_AO] = &mxc_ao,

Is there any parent/child relationship between mmcx/mxc and other domains?

> +	[SA8775P_MX] = &mx,
> +	[SA8775P_MX_AO] = &mx_ao,
> +	[SA8775P_NSP0] = &nsp0,
> +	[SA8775P_NSP1] = &nsp1,
> +};
> +
> +static const struct rpmhpd_desc sa8775p_desc = {
> +	.rpmhpds = sa8775p_rpmhpds,
> +	.num_pds = ARRAY_SIZE(sa8775p_rpmhpds),
> +};
> +
>   /* SDM670 RPMH powerdomains */
>   static struct rpmhpd *sdm670_rpmhpds[] = {
>   	[SDM670_CX] = &cx_w_mx_parent,
> @@ -487,6 +520,7 @@ static const struct rpmhpd_desc sc8280xp_desc = {
>   static const struct of_device_id rpmhpd_match_table[] = {
>   	{ .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc },
>   	{ .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc },
> +	{ .compatible = "qcom,sa8775p-rpmhpd", .data = &sa8775p_desc },
>   	{ .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc },
>   	{ .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc },
>   	{ .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc },

On 09/01/2023 19:44, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> This adds basic support for the Qualcomm sa8775p platform and its reference
> board: sa8775p-ride. The dtsi contains basic SoC description required for
> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
> sa8775p-ride board. There are three new drivers required to boot the board:
> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
> to existing code. More support is coming up.
> 
> Bartosz Golaszewski (15):
>    dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p
>    arm64: defconfig: enable the clock driver for Qualcomm SA8775P
>      platforms
>    dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p
>    clk: qcom: rpmh: add clocks for sa8775p
>    dt-bindings: interconnect: qcom: document the interconnects for
>      sa8775p
>    arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P
>    dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm
>    arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P
>      platforms
>    dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
>    dt-bindings: power: qcom,rpmpd: document sa8775p
>    soc: qcom: rmphpd: add power domains for sa8775p
>    dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P
>    iommu: arm-smmu: qcom: add support for sa8775p
>    dt-bindings: arm: qcom: document the sa8775p reference board
>    arm64: dts: qcom: add initial support for qcom sa8775p-ride
> 
> Shazad Hussain (2):
>    clk: qcom: add the GCC driver for sa8775p

This patch didn't make it to the list. Please check if you can fix or 
split it somehow?

On 9.01.2023 21:13, Dmitry Baryshkov wrote:
> On 09/01/2023 19:44, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>
>> This adds basic support for the Qualcomm sa8775p platform and its reference
>> board: sa8775p-ride. The dtsi contains basic SoC description required for
>> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
>> sa8775p-ride board. There are three new drivers required to boot the board:
>> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
>> to existing code. More support is coming up.
>>
>> Bartosz Golaszewski (15):
>>    dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p
>>    arm64: defconfig: enable the clock driver for Qualcomm SA8775P
>>      platforms
>>    dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p
>>    clk: qcom: rpmh: add clocks for sa8775p
>>    dt-bindings: interconnect: qcom: document the interconnects for
>>      sa8775p
>>    arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P
>>    dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm
>>    arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P
>>      platforms
>>    dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
>>    dt-bindings: power: qcom,rpmpd: document sa8775p
>>    soc: qcom: rmphpd: add power domains for sa8775p
>>    dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P
>>    iommu: arm-smmu: qcom: add support for sa8775p
>>    dt-bindings: arm: qcom: document the sa8775p reference board
>>    arm64: dts: qcom: add initial support for qcom sa8775p-ride
>>
>> Shazad Hussain (2):
>>    clk: qcom: add the GCC driver for sa8775p
> 
> This patch didn't make it to the list. Please check if you can fix or split it somehow?
It's a known issue with lists clipping messages that are too long.
I'll forward it to you.

Konrad
>

On 09/01/2023 22:59, Konrad Dybcio wrote:
> 
> 
> On 9.01.2023 21:13, Dmitry Baryshkov wrote:
>> On 09/01/2023 19:44, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>>
>>> This adds basic support for the Qualcomm sa8775p platform and its reference
>>> board: sa8775p-ride. The dtsi contains basic SoC description required for
>>> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
>>> sa8775p-ride board. There are three new drivers required to boot the board:
>>> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
>>> to existing code. More support is coming up.
>>>
>>> Bartosz Golaszewski (15):
>>>     dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p
>>>     arm64: defconfig: enable the clock driver for Qualcomm SA8775P
>>>       platforms
>>>     dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p
>>>     clk: qcom: rpmh: add clocks for sa8775p
>>>     dt-bindings: interconnect: qcom: document the interconnects for
>>>       sa8775p
>>>     arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P
>>>     dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm
>>>     arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P
>>>       platforms
>>>     dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
>>>     dt-bindings: power: qcom,rpmpd: document sa8775p
>>>     soc: qcom: rmphpd: add power domains for sa8775p
>>>     dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P
>>>     iommu: arm-smmu: qcom: add support for sa8775p
>>>     dt-bindings: arm: qcom: document the sa8775p reference board
>>>     arm64: dts: qcom: add initial support for qcom sa8775p-ride
>>>
>>> Shazad Hussain (2):
>>>     clk: qcom: add the GCC driver for sa8775p
>>
>> This patch didn't make it to the list. Please check if you can fix or split it somehow?
> It's a known issue with lists clipping messages that are too long.
> I'll forward it to you.

Thank you!

On 09/01/2023 19:58, Konrad Dybcio wrote:
> 
> 
> On 9.01.2023 18:44, Bartosz Golaszewski wrote:
>> From: Shazad Hussain <quic_shazhuss@quicinc.com>
>>
>> Add support for the Global Clock Controller found in the QTI SA8775P
>> platforms.
>>
>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>> [Bartosz: made the driver ready for upstream]
>> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> ---
> [...]
>

As the driver didn't get to the list, I'll comment OOB.

Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks).

On Mon, Jan 9, 2023 at 6:45 PM Bartosz Golaszewski <brgl@bgdev.pl> wrote:

> From: Yadu MG <quic_ymg@quicinc.com>
>
> Add support for Lemans TLMM configuration and control via the pinctrl
> framework.
>
> Signed-off-by: Yadu MG <quic_ymg@quicinc.com>
> Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com>
> [Bartosz: made the driver ready for upstream]
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

Overall looks good, Konrad has some comments to be addressed.
Is this something I can just apply in the next iteration?

Yours,
Linus Walleij

On Mon, Jan 09, 2023 at 06:45:03PM +0100, Bartosz Golaszewski wrote:
[..]
> +enum sa8775p_functions {
> +	msm_mux_gpio,
> +	msm_mux_atest_char,
> +	msm_mux_atest_char0,
> +	msm_mux_atest_char1,
> +	msm_mux_atest_char2,
> +	msm_mux_atest_char3,
> +	msm_mux_atest_usb2,
> +	msm_mux_atest_usb20,
> +	msm_mux_atest_usb21,
> +	msm_mux_atest_usb22,
> +	msm_mux_atest_usb23,

Please squash these to a single msm_mux_atest.

> +	msm_mux_audio_ref,
> +	msm_mux_cam_mclk,
> +	msm_mux_cci_async,
> +	msm_mux_cci_i2c,
> +	msm_mux_cci_timer0,
> +	msm_mux_cci_timer1,
> +	msm_mux_cci_timer2,
> +	msm_mux_cci_timer3,
> +	msm_mux_cci_timer4,
> +	msm_mux_cci_timer5,
> +	msm_mux_cci_timer6,
> +	msm_mux_cci_timer7,
> +	msm_mux_cci_timer8,
> +	msm_mux_cci_timer9,
> +	msm_mux_cri_trng,
> +	msm_mux_cri_trng0,
> +	msm_mux_cri_trng1,
> +	msm_mux_dbg_out,
> +	msm_mux_ddr_bist,
> +	msm_mux_ddr_pxi0,
> +	msm_mux_ddr_pxi1,
> +	msm_mux_ddr_pxi2,
> +	msm_mux_ddr_pxi3,
> +	msm_mux_ddr_pxi4,
> +	msm_mux_ddr_pxi5,
> +	msm_mux_edp0_hot,
> +	msm_mux_edp0_lcd,
> +	msm_mux_edp1_hot,
> +	msm_mux_edp1_lcd,
> +	msm_mux_edp2_hot,
> +	msm_mux_edp2_lcd,
> +	msm_mux_edp3_hot,
> +	msm_mux_edp3_lcd,
> +	msm_mux_emac0_mcg0,
> +	msm_mux_emac0_mcg1,
> +	msm_mux_emac0_mcg2,
> +	msm_mux_emac0_mcg3,
> +	msm_mux_emac0_mdc,
> +	msm_mux_emac0_mdio,
> +	msm_mux_emac0_ptp,

msm_mux_emac0

> +	msm_mux_emac1_mcg0,
> +	msm_mux_emac1_mcg1,
> +	msm_mux_emac1_mcg2,
> +	msm_mux_emac1_mcg3,
> +	msm_mux_emac1_mdc,
> +	msm_mux_emac1_mdio,
> +	msm_mux_emac1_ptp,

msm_mux_emac1

> +	msm_mux_gcc_gp1,
> +	msm_mux_gcc_gp2,
> +	msm_mux_gcc_gp3,
> +	msm_mux_gcc_gp4,
> +	msm_mux_gcc_gp5,
> +	msm_mux_hs0_mi2s,
> +	msm_mux_hs1_mi2s,
> +	msm_mux_hs2_mi2s,
> +	msm_mux_ibi_i3c,
> +	msm_mux_jitter_bist,
> +	msm_mux_mdp0_vsync0,
> +	msm_mux_mdp0_vsync1,
> +	msm_mux_mdp0_vsync2,
> +	msm_mux_mdp0_vsync3,
> +	msm_mux_mdp0_vsync4,
> +	msm_mux_mdp0_vsync5,
> +	msm_mux_mdp0_vsync6,
> +	msm_mux_mdp0_vsync7,
> +	msm_mux_mdp0_vsync8,
> +	msm_mux_mdp1_vsync0,
> +	msm_mux_mdp1_vsync1,
> +	msm_mux_mdp1_vsync2,
> +	msm_mux_mdp1_vsync3,
> +	msm_mux_mdp1_vsync4,
> +	msm_mux_mdp1_vsync5,
> +	msm_mux_mdp1_vsync6,
> +	msm_mux_mdp1_vsync7,
> +	msm_mux_mdp1_vsync8,
> +	msm_mux_mdp_vsync,
> +	msm_mux_mi2s1_data0,
> +	msm_mux_mi2s1_data1,
> +	msm_mux_mi2s1_sck,
> +	msm_mux_mi2s1_ws,
> +	msm_mux_mi2s2_data0,
> +	msm_mux_mi2s2_data1,
> +	msm_mux_mi2s2_sck,
> +	msm_mux_mi2s2_ws,
> +	msm_mux_mi2s_mclk0,
> +	msm_mux_mi2s_mclk1,
> +	msm_mux_pcie0_clkreq,
> +	msm_mux_pcie1_clkreq,
> +	msm_mux_phase_flag0,
> +	msm_mux_phase_flag1,
> +	msm_mux_phase_flag10,
> +	msm_mux_phase_flag11,
> +	msm_mux_phase_flag12,
> +	msm_mux_phase_flag13,
> +	msm_mux_phase_flag14,
> +	msm_mux_phase_flag15,
> +	msm_mux_phase_flag16,
> +	msm_mux_phase_flag17,
> +	msm_mux_phase_flag18,
> +	msm_mux_phase_flag19,
> +	msm_mux_phase_flag2,
> +	msm_mux_phase_flag20,
> +	msm_mux_phase_flag21,
> +	msm_mux_phase_flag22,
> +	msm_mux_phase_flag23,
> +	msm_mux_phase_flag24,
> +	msm_mux_phase_flag25,
> +	msm_mux_phase_flag26,
> +	msm_mux_phase_flag27,
> +	msm_mux_phase_flag28,
> +	msm_mux_phase_flag29,
> +	msm_mux_phase_flag3,
> +	msm_mux_phase_flag30,
> +	msm_mux_phase_flag31,
> +	msm_mux_phase_flag4,
> +	msm_mux_phase_flag5,
> +	msm_mux_phase_flag6,
> +	msm_mux_phase_flag7,
> +	msm_mux_phase_flag8,
> +	msm_mux_phase_flag9,

msm_mux_phase_flag

> +	msm_mux_pll_bist,
> +	msm_mux_pll_clk,
> +	msm_mux_prng_rosc0,
> +	msm_mux_prng_rosc1,
> +	msm_mux_prng_rosc2,
> +	msm_mux_prng_rosc3,
> +	msm_mux_qdss_cti,
> +	msm_mux_qdss_gpio,
> +	msm_mux_qdss_gpio0,
> +	msm_mux_qdss_gpio1,
> +	msm_mux_qdss_gpio10,
> +	msm_mux_qdss_gpio11,
> +	msm_mux_qdss_gpio12,
> +	msm_mux_qdss_gpio13,
> +	msm_mux_qdss_gpio14,
> +	msm_mux_qdss_gpio15,
> +	msm_mux_qdss_gpio2,
> +	msm_mux_qdss_gpio3,
> +	msm_mux_qdss_gpio4,
> +	msm_mux_qdss_gpio5,
> +	msm_mux_qdss_gpio6,
> +	msm_mux_qdss_gpio7,
> +	msm_mux_qdss_gpio8,
> +	msm_mux_qdss_gpio9,

msm_mux_qdss

> +	msm_mux_qup0_se0,
> +	msm_mux_qup0_se1,
> +	msm_mux_qup0_se2,
> +	msm_mux_qup0_se3,
> +	msm_mux_qup0_se4,
> +	msm_mux_qup0_se5,
> +	msm_mux_qup1_se0,
> +	msm_mux_qup1_se1,
> +	msm_mux_qup1_se2,
> +	msm_mux_qup1_se3,
> +	msm_mux_qup1_se4,
> +	msm_mux_qup1_se5,
> +	msm_mux_qup1_se6,
> +	msm_mux_qup2_se0,
> +	msm_mux_qup2_se1,
> +	msm_mux_qup2_se2,
> +	msm_mux_qup2_se3,
> +	msm_mux_qup2_se4,
> +	msm_mux_qup2_se5,
> +	msm_mux_qup2_se6,
> +	msm_mux_qup3_se0,
> +	msm_mux_sail_top,
> +	msm_mux_sailss_emac0,
> +	msm_mux_sailss_ospi,
> +	msm_mux_sgmii_phy,
> +	msm_mux_tb_trig,
> +	msm_mux_tgu_ch0,
> +	msm_mux_tgu_ch1,
> +	msm_mux_tgu_ch2,
> +	msm_mux_tgu_ch3,
> +	msm_mux_tgu_ch4,
> +	msm_mux_tgu_ch5,
> +	msm_mux_tsense_pwm1,
> +	msm_mux_tsense_pwm2,
> +	msm_mux_tsense_pwm3,
> +	msm_mux_tsense_pwm4,
> +	msm_mux_usb2phy_ac,
> +	msm_mux_vsense_trigger,
> +	msm_mux__,
> +};
> +
[..]
> +static const struct msm_pingroup sa8775p_groups[] = {
> +	[0] = PINGROUP(0, _, _, _, _, _, _, _, _, _),
> +	[1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _),
> +	[2] = PINGROUP(2, _, _, _, _, _, _, _, _, _),
> +	[3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _),
> +	[4] = PINGROUP(4, _, _, _, _, _, _, _, _, _),
> +	[5] = PINGROUP(5, _, _, _, _, _, _, _, _, _),
> +	[6] = PINGROUP(6, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _, _),

How is it possible to select the first or the second one of these
functions when they are named the same?

> +	[7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _),
> +	[8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _),
> +	[9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _),
> +	[10] = PINGROUP(10, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _),
> +	[11] = PINGROUP(11, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _),
> +	[12] = PINGROUP(12, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp,
> +			emac0_mcg0, _, _, _),
> +	[13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _),
> +	[14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _),
> +	[15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _),
> +	[16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _),
> +	[17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _),
> +	[18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _),
> +	[19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _),
> +	[20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _),
> +	[21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _),
> +	[22] = PINGROUP(22, qup0_se0, qdss_gpio15, _, _, _, _, _, _, _),
> +	[23] = PINGROUP(23, qup0_se0, qdss_gpio14, _, _, _, _, _, _, _),
> +	[24] = PINGROUP(24, qup0_se1, qdss_gpio13, _, _, _, _, _, _, _),
> +	[25] = PINGROUP(25, qup0_se1, phase_flag31, _, qdss_gpio12, _, _, _, _, _),
> +	[26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag30, _, _, _, _, _),
> +	[27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag29, _, atest_char, _, _, _, _),
> +	[28] = PINGROUP(28, qup0_se3, phase_flag28, _, qdss_gpio11, _, _, _, _, _),
> +	[29] = PINGROUP(29, qup0_se3, phase_flag27, _, qdss_gpio10, _, _, _, _, _),
> +	[30] = PINGROUP(30, qup0_se3, phase_flag26, _, qdss_gpio9, _, _, _, _, _),
> +	[31] = PINGROUP(31, qup0_se3, phase_flag25, _, qdss_gpio8, _, _, _, _, _),
> +	[32] = PINGROUP(32, qup0_se4, phase_flag24, _, _, _, _, _, _, _),
> +	[33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _,	_),
> +	[34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _,	_),
> +	[35] = PINGROUP(35, qup0_se4, phase_flag23, _, _, _, _, _, _, _),
> +	[36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag22, tgu_ch2, _, _, _, _, _),
> +	[37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag21, tgu_ch3, _, _, _, _, _),
> +	[38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag20, tgu_ch4, _, _, _, _),
> +	[39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag19, tgu_ch5, _, _, _, _),
> +	[40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _),
> +	[41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _),
> +	[42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _),
> +	[43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _),
> +	[44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _),
> +	[45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _),
> +	[46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _),
> +	[47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _),
> +	[48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _),
> +	[49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _),
> +	[50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _),
> +	[51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _),
> +	[52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7,	gcc_gp2, _, ddr_pxi1, _, _),
> +	[53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _),
> +	[54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _),
> +	[55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _),
> +	[56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag18,
> +			ddr_bist, _, _, _),
> +	[57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0,
> +			phase_flag17, ddr_bist, _, _),
> +	[58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char1, _, _, _),
> +	[59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char0, _, _, _),
> +	[60] = PINGROUP(60, cci_i2c, qdss_gpio0, _, _, _, _, _, _, _),
> +	[61] = PINGROUP(61, cci_i2c, qdss_gpio1, _, _, _, _, _, _, _),
> +	[62] = PINGROUP(62, cci_i2c, qdss_gpio2, _, _, _, _, _, _, _),
> +	[63] = PINGROUP(63, cci_i2c, qdss_gpio3, _, _, _, _, _, _, _),
> +	[64] = PINGROUP(64, cci_i2c, qdss_gpio4, _, _, _, _, _, _, _),
> +	[65] = PINGROUP(65, cci_i2c, qdss_gpio5, _, _, _, _, _, _, _),
> +	[66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio6, _, _, _, _, _, _),
> +	[67] = PINGROUP(67, cci_i2c, qdss_gpio7, _, _, _, _, _, _, _),
> +	[68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _),
> +	[69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _),
> +	[70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _),
> +	[71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _),
> +	[72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _),
> +	[73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _),
> +	[74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _),
> +	[75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _),
> +	[76] = PINGROUP(76, _, _, _, _, _, _, _, _, _),
> +	[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
> +	[78] = PINGROUP(78, _, _, _, _, _, _, _, _, _),
> +	[79] = PINGROUP(79, _, _, _, _, _, _, _, _, _),
> +	[80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _),
> +	[81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _),
> +	[82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _),
> +	[83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _),
> +	[84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _),
> +	[85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _),
> +	[86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _),
> +	[87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb20, ddr_pxi3, _, _, _, _, _),
> +	[88] = PINGROUP(88, qup2_se2, _, atest_usb21, ddr_pxi3, _, _, _, _, _),
> +	[89] = PINGROUP(89, qup2_se2, _, atest_usb22, ddr_pxi4, atest_char3, _, _, _, _),
> +	[90] = PINGROUP(90, qup2_se2, _, atest_usb23, ddr_pxi4, atest_char2, _, _, _, _),
> +	[91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb20, _, _, _, _, _),
> +	[92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb21, _, _, _, _, _),
> +	[93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb22, _, _, _, _, _),
> +	[94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb23, _, _, _, _, _),
> +	[95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb20, _, _, _, _, _),
> +	[96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb21, _, _, _, _, _),
> +	[97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb22, _, _, _, _),
> +	[98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag16, cri_trng1, _, _, _, _, _),
> +	[99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag15, cri_trng, _, _, _, _, _),
> +	[100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _),
> +	[101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _),
> +	[102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _),
> +	[103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _),
> +	[104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _),
> +	[105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb23, _, _, _, _, _),
> +	[106] = PINGROUP(106, mi2s1_sck, phase_flag14, _, qdss_gpio8, _, _, _, _, _),
> +	[107] = PINGROUP(107, mi2s1_ws, phase_flag13, _, qdss_gpio9, _, _, _, _, _),
> +	[108] = PINGROUP(108, mi2s1_data0, phase_flag12, _, qdss_gpio10, _, _, _, _, _),
> +	[109] = PINGROUP(109, mi2s1_data1, phase_flag11, _, qdss_gpio11, _, _, _, _, _),
> +	[110] = PINGROUP(110, mi2s2_sck, phase_flag10, _, qdss_gpio12, _, _, _, _, _),
> +	[111] = PINGROUP(111, mi2s2_ws, phase_flag9, _, qdss_gpio13, vsense_trigger, _, _, _, _),
> +	[112] = PINGROUP(112, mi2s2_data0, phase_flag8, _, qdss_gpio14, _, _, _, _, _),
> +	[113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag7, _, qdss_gpio15, _, _, _, _),
> +	[114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag6, _, qdss_gpio, _, _, _, _),
> +	[115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio0, _, _, _, _, _, _),
> +	[116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio1, _, _, _, _, _, _),
> +	[117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio2, _, _, _, _, _),
> +	[118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio3, ddr_pxi5, _, _, _, _, _),
> +	[119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio4, ddr_pxi5, _, _, _, _, _),
> +	[120] = PINGROUP(120, hs1_mi2s, phase_flag5, _, qdss_gpio5, _, _, _, _, _),
> +	[121] = PINGROUP(121, hs1_mi2s, phase_flag4, _, qdss_gpio6, _, _, _, _, _),
> +	[122] = PINGROUP(122, hs2_mi2s, phase_flag3, _, qdss_gpio7, _, _, _, _, _),
> +	[123] = PINGROUP(123, hs2_mi2s, phase_flag2, _, _, _, _, _, _, _),
> +	[124] = PINGROUP(124, hs2_mi2s, phase_flag1, _, _, _, _, _, _, _),
> +	[125] = PINGROUP(125, hs2_mi2s, phase_flag0, _, _, _, _, _, _, _),
> +	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
> +	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _),
> +	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _),
> +	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
> +	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
> +	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
> +	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
> +	[133] = PINGROUP(133, _, _, _, _, _, _, _, _, _),
> +	[134] = PINGROUP(134, _, _, _, _, _, _, _, _, _),
> +	[135] = PINGROUP(135, _, _, _, _, _, _, _, _, _),
> +	[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _),
> +	[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _),
> +	[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _),
> +	[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
> +	[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _),
> +	[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
> +	[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
> +	[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
> +	[144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _),
> +	[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
> +	[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
> +	[147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
> +	[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
> +	[149] = UFS_RESET(ufs_reset, 0x1a2000),
> +	[150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0),
> +	[151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6),
> +	[152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3),
> +	[153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0),
> +};
> +
> +static const struct msm_pinctrl_soc_data sa8775p_pinctrl = {
> +	.pins = sa8775p_pins,
> +	.npins = ARRAY_SIZE(sa8775p_pins),
> +	.functions = sa8775p_functions,
> +	.nfunctions = ARRAY_SIZE(sa8775p_functions),
> +	.groups = sa8775p_groups,
> +	.ngroups = ARRAY_SIZE(sa8775p_groups),
> +	.ngpios = 150,
> +};
> +
> +static int sa8775p_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return msm_pinctrl_probe(pdev, &sa8775p_pinctrl);
> +}
> +
> +static const struct of_device_id sa8775p_pinctrl_of_match[] = {
> +	{ .compatible = "qcom,sa8775p-pinctrl", },

qcom,sa8775p-tlmm

> +	{ },
> +};
> +
> +static struct platform_driver sa8775p_pinctrl_driver = {
> +	.driver = {
> +		.name = "sa8775p-pinctrl",
> +		.of_match_table = sa8775p_pinctrl_of_match,
> +	},
> +	.probe = sa8775p_pinctrl_probe,
> +	.remove = msm_pinctrl_remove,
> +};
> +
> +static int __init sa8775p_pinctrl_init(void)
> +{
> +	return platform_driver_register(&sa8775p_pinctrl_driver);
> +}
> +arch_initcall(sa8775p_pinctrl_init);
> +
> +static void __exit sa8775p_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&sa8775p_pinctrl_driver);
> +}
> +module_exit(sa8775p_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("QTI SA8775P pinctrl driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match);

Please move this next to the of_match table.

Regards,
Bjorn


> -- 
> 2.37.2
>

On Mon, 9 Jan 2023 18:44:53 +0100, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> This adds basic support for the Qualcomm sa8775p platform and its reference
> board: sa8775p-ride. The dtsi contains basic SoC description required for
> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
> sa8775p-ride board. There are three new drivers required to boot the board:
> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
> to existing code. More support is coming up.
> 
> [...]

Applied, thanks!

[13/18] dt-bindings: power: qcom,rpmpd: document sa8775p
        commit: b4f0370d3ce276397f5c48af99d0b77548825eb1
[14/18] soc: qcom: rmphpd: add power domains for sa8775p
        commit: 91e910adc59a6954e475dd2d6a4534ac56dd8eed

Best regards,

On 1/9/2023 10:34 AM, Krzysztof Kozlowski wrote:
> On 09/01/2023 18:45, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>
>> This adds basic support for the Qualcomm sa8775p platform and the
>> reference board: sa8775p-ride. The dt files describe the basics of the
>> SoC and enable booting to shell.
>>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile         |   1 +
>>   arch/arm64/boot/dts/qcom/sa8775p-ride.dts |  39 +
>>   arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 841 ++++++++++++++++++++++
>>   3 files changed, 881 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..39b8206f7131 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5-vision-mezzanine.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sa8155p-adp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sa8295p-adp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sa8540p-ride.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-coachz-r1-lte.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>> new file mode 100644
>> index 000000000000..d4dae32a84cc
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>> @@ -0,0 +1,39 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "sa8775p.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm SA8875P Ride";
>> +	compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
>> +
>> +	aliases {
>> +		serial0 = &uart10;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&qupv3_id_1 {
>> +	status = "okay";
>> +};
>> +
>> +&uart10 {
>> +	compatible = "qcom,geni-debug-uart";
>> +	status = "okay";
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&qup_uart10_state>;
>> +};
>> +
>> +&tlmm {
>> +	qup_uart10_state: qup_uart10_state {
> 
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
> 
>> +		pins = "gpio46", "gpio47";
>> +		function = "qup1_se3";
>> +	};
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> new file mode 100644
>> index 000000000000..1a3b11628e38
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -0,0 +1,841 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> 
> Why GPL-2.0-only? Isn't this based on other code which is either
> dual-licensed or BSD license?
> 
>> +/*
>> + * Copyright (c) 2023, Linaro Limited
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-sa8775p.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			#clock-cells = <0>;
> 
> Your board needs clock frequency.
> 
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			#clock-cells = <0>;
>> +			clock-frequency = <32764>;
> 
> Usual comment: this (entire clock or at least its frequency) is usually
> not a property of a SoC, but board. Did something change here in SA8775?
> 
> 
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <2>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +			L2_0: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_0>;
> 
> Messed indentation.
> 
>> +				L3_0: l3-cache {
>> +				      compatible = "cache";
>> +				};
>> +			};
>> +		};
>> +
>> +		CPU1: cpu@100 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x100>;
>> +			enable-method = "psci";
>> +			cpu-release-addr = <0x0 0x90000000>;
>> +			next-level-cache = <&L2_1>;
>> +			L2_1: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_0>;
>> +			};
>> +		};
>> +
>> +		CPU2: cpu@200 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x200>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_2>;
>> +			L2_2: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_0>;
>> +			};
>> +		};
>> +
>> +		CPU3: cpu@300 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x300>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_3>;
>> +			L2_3: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_0>;
>> +			};
>> +		};
>> +
>> +		CPU4: cpu@10000 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x10000>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_4>;
>> +			L2_4: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_1>;
>> +				L3_1: l3-cache {
>> +				      compatible = "cache";
>> +				};
>> +
>> +			};
>> +		};
>> +
>> +		CPU5: cpu@10100 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x10100>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_5>;
>> +			L2_5: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_1>;
>> +			};
>> +		};
>> +
>> +		CPU6: cpu@10200 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x10200>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_6>;
>> +			L2_6: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_1>;
>> +			};
>> +		};
>> +
>> +		CPU7: cpu@10300 {
>> +			device_type = "cpu";
>> +			compatible = "qcom,kryo";
>> +			reg = <0x0 0x10300>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_7>;
>> +			L2_7: l2-cache {
>> +			      compatible = "cache";
>> +			      next-level-cache = <&L3_1>;
>> +			};
>> +		};
>> +
>> +		cpu-map {
>> +			cluster0 {
>> +				core0 {
>> +					cpu = <&CPU0>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&CPU1>;
>> +				};
>> +
>> +				core2 {
>> +					cpu = <&CPU2>;
>> +				};
>> +
>> +				core3 {
>> +					cpu = <&CPU3>;
>> +				};
>> +			};
>> +
>> +			cluster1 {
>> +				core0 {
>> +					cpu = <&CPU4>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&CPU5>;
>> +				};
>> +
>> +				core2 {
>> +					cpu = <&CPU6>;
>> +				};
>> +
>> +				core3 {
>> +					cpu = <&CPU7>;
>> +				};
>> +			};
>> +		};
>> +	};
>> +
>> +	/* Will be updated by the bootloader. */
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0 0 0 0>;
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		sail_ss_mem: sail_ss_region@80000000 {
> 
> No underscores in node names.
> 
> (...)
> 
>> +
>> +	qup_opp_table_100mhz: qup-100mhz-opp-table {
> 
> opp-table-....
> 
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
> 
>> +		compatible = "operating-points-v2";
>> +
>> +		opp-100000000 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			required-opps = <&rpmhpd_opp_svs_l1>;
>> +		};
>> +	};
>> +
>> +	soc: soc@0 {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;

Can you please update address-cells and size-cells as <2> and update sub 
nodes accordingly?
                 #address-cells = <2>;
                 #size-cells = <2>;

>> +		ranges = <0 0 0 0xffffffff>;
>> +
>> +		gcc: clock-controller@100000 {
>> +			compatible = "qcom,gcc-sa8775p";
>> +			reg = <0x100000 0xc7018>;
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +			#power-domain-cells = <1>;
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +				 <&sleep_clk>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>, /* TODO: usb_0_ssphy */
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>;
>> +			power-domains = <&rpmhpd SA8775P_CX>;
>> +		};
>> +
>> +		ipcc: mailbox@408000 {
>> +			compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
>> +			reg = <0x408000 0x1000>;
>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			#mbox-cells = <2>;
>> +		};
>> +
>> +		aggre1_noc:interconnect-aggre1-noc {
> 
> Missing space after :
> 
>> +			compatible = "qcom,sa8775p-aggre1-noc";
> 
> This does not match your bindings, so nothing here was tested against
> your own files which you sent.
> 
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		aggre2_noc: interconnect-aggre2-noc {
>> +			compatible = "qcom,sa8775p-aggre2-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		clk_virt: interconnect-clk-virt {
>> +			compatible = "qcom,sa8775p-clk-virt";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		config_noc: interconnect-config-noc {
>> +			compatible = "qcom,sa8775p-config-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		dc_noc: interconnect-dc-noc {
>> +			compatible = "qcom,sa8775p-dc-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		gem_noc: interconnect-gem-noc {
>> +			compatible = "qcom,sa8775p-gem-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		gpdsp_anoc: interconnect-gpdsp-anoc {
>> +			compatible = "qcom,sa8775p-gpdsp-anoc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		lpass_ag_noc: interconnect-lpass-ag-noc {
>> +			compatible = "qcom,sa8775p-lpass-ag-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		mc_virt: interconnect-mc-virt {
>> +			compatible = "qcom,sa8775p-mc-virt";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		mmss_noc: interconnect-mmss-noc {
>> +			compatible = "qcom,sa8775p-mmss-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		nspa_noc: interconnect-nspa-noc {
>> +			compatible = "qcom,sa8775p-nspa-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		nspb_noc: interconnect-nspb-noc {
>> +			compatible = "qcom,sa8775p-nspb-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		pcie_anoc: interconnect-pcie-anoc {
>> +			compatible = "qcom,sa8775p-pcie-anoc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		system_noc: interconnect-system-noc {
>> +			compatible = "qcom,sa8775p-system-noc";
>> +			#interconnect-cells = <2>;
>> +			qcom,bcm-voters = <&apps_bcm_voter>;
>> +		};
>> +
>> +		intc: interrupt-controller@17a00000 {
>> +			compatible = "arm,gic-v3";
>> +			#interrupt-cells = <3>;
>> +			interrupt-controller;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			#redistributor-regions = <1>;
>> +			redistributor-stride = <0x0 0x20000>;
>> +			reg = <0x17a00000 0x10000>,     /* GICD */
>> +			      <0x17a60000 0x100000>;    /* GICR * 8 */
> 
> Compatible goes first, then reg, then ranges.
> 
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>> +		apps_rsc: rsc@18200000 {
>> +			compatible = "qcom,rpmh-rsc";
>> +			reg = <0x18200000 0x10000>,
>> +			      <0x18210000 0x10000>,
>> +			      <0x18220000 0x10000>;
>> +			reg-names = "drv-0", "drv-1", "drv-2";
>> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> +			      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> +			      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> +			qcom,tcs-offset = <0xd00>;
>> +			qcom,drv-id = <2>;
>> +			qcom,tcs-config = <ACTIVE_TCS 2>,
>> +					  <SLEEP_TCS 3>,
>> +					  <WAKE_TCS 3>,
>> +					  <CONTROL_TCS 0>;
>> +			label = "apps_rsc";
>> +
>> +			apps_bcm_voter: bcm_voter {
> 
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
> 
>> +				compatible = "qcom,bcm-voter";
>> +			};
>> +
>> +			rpmhcc: clock-controller {
>> +				compatible = "qcom,sa8775p-rpmh-clk";
>> +				#clock-cells = <1>;
>> +				clock-names = "xo";
>> +				clocks = <&xo_board_clk>;
>> +			};
>> +
>> +			rpmhpd: power-controller {
>> +				compatible = "qcom,sa8775p-rpmhpd";
>> +				#power-domain-cells = <1>;
>> +				operating-points-v2 = <&rpmhpd_opp_table>;
>> +
>> +				rpmhpd_opp_table: opp-table {
>> +					compatible = "operating-points-v2";
>> +
>> +					rpmhpd_opp_ret: opp1 {
> 
> opp-0
> (so numbering from 0 and hyphen)
> 
>> +						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
>> +					};
>> +
>> +					rpmhpd_opp_min_svs: opp2 {
> 
> opp-1
> 
>> +						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>> +					};
>> +
>> +					rpmhpd_opp_low_svs: opp3 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +					};
>> +
>> +					rpmhpd_opp_svs: opp4 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> +					};
>> +
>> +					rpmhpd_opp_svs_l1: opp5 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> +					};
>> +
>> +					rpmhpd_opp_nom: opp6 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> +					};
>> +
>> +					rpmhpd_opp_nom_l1: opp7 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> +					};
>> +
>> +					rpmhpd_opp_nom_l2: opp8 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
>> +					};
>> +
>> +					rpmhpd_opp_turbo: opp9 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>> +					};
>> +
>> +					rpmhpd_opp_turbo_l1: opp10 {
>> +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>> +					};
>> +				};
>> +			};
>> +		};
>> +
>> +		arch_timer: timer {
>> +			compatible = "arm,armv8-timer";
>> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> +				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> +				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> +				     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> +			clock-frequency = <19200000>;
>> +		};
>> +
>> +		memtimer: timer@17c20000 {
> 
> Why this one is outside of soc node? Or are we inside soc? But then
> ARMv8 timer cannot be here... dtbs W=1 would warn you, wouldn't it?
> 
> 
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			compatible = "arm,armv7-timer-mem";
> 
> Weird order of properties.
> 
>> +			reg = <0x17c20000 0x1000>;
>> +			clock-frequency = <19200000>;
>> +
>> +			frame@17c21000 {
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c21000 0x1000>,
>> +				      <0x17c22000 0x1000>;
>> +			};
>> +
>> +			frame@17c23000 {
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c23000 0x1000>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@17c25000 {
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c25000 0x1000>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@17c27000 {
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c27000 0x1000>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@17c29000 {
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c29000 0x1000>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@17c2b000 {
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c2b000 0x1000>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@17c2d000 {
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				reg = <0x17c2d000 0x1000>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +
>> +		tcsr_mutex: hwlock@1f40000 {
>> +			compatible = "qcom,tcsr-mutex";
>> +			reg = <0x1f40000 0x20000>;
>> +			#hwlock-cells = <1>;
>> +		};
>> +
>> +		tlmm: pinctrl@f000000 {
>> +			compatible = "qcom,sa8775p-pinctrl";
>> +			reg = <0xf000000 0x1000000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 149>;
>> +		};
>> +
>> +		qcom-wdt@17c10000 {
> 
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> 
>> +			compatible = "qcom,kpss-wdt";
>> +			reg = <0x17c10000 0x1000>;
>> +			clocks = <&sleep_clk>;
>> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>> +		qupv3_id_1: geniqup@ac0000 {
>> +			compatible = "qcom,geni-se-qup";
>> +			reg = <0xac0000 0x6000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-names = "m-ahb", "s-ahb";
>> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> +			iommus = <&apps_smmu 0x443 0x0>;
>> +			status = "disabled";
>> +
>> +			uart10: serial@a8c000 {
>> +				compatible = "qcom,geni-uart";
>> +				reg = <0xa8c000 0x4000>;
>> +				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
>> +				clock-names = "se";
>> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
>> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
>> +						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
>> +						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
>> +				power-domains = <&rpmhpd SA8775P_CX>;
>> +				operating-points-v2 = <&qup_opp_table_100mhz>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +
>> +		apps_smmu: apps-smmu@15000000 {
> 
> iommu, node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> 
> and probably also fails dtbs_check...
> 
>> +			compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500";
>> +			reg = <0x15000000 0x100000>, <0x15182000 0x28>;
>> +			reg-names = "base", "tcu-base";
>> +			#iommu-cells = <2>;
>> +			qcom,skip-init;
>> +			qcom,use-3-lvl-tables;
>> +			#global-interrupts = <2>;
>> +			#size-cells = <1>;
> 
> Best regards,
> Krzysztof
> 
> 
>

On Mon, Jan 9, 2023 at 10:06 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 09/01/2023 19:58, Konrad Dybcio wrote:
> >
> >
> > On 9.01.2023 18:44, Bartosz Golaszewski wrote:
> >> From: Shazad Hussain <quic_shazhuss@quicinc.com>
> >>
> >> Add support for the Global Clock Controller found in the QTI SA8775P
> >> platforms.
> >>
> >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> >> [Bartosz: made the driver ready for upstream]
> >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >> ---
> > [...]
> >
>
> As the driver didn't get to the list, I'll comment OOB.
>
> Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks).
>

Looks like it's impossible for this platform as the PCIe PIPE clocks
have two parents.

Bart

On Tue, 17 Jan 2023 at 14:44, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>
> On Mon, Jan 9, 2023 at 10:06 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On 09/01/2023 19:58, Konrad Dybcio wrote:
> > >
> > >
> > > On 9.01.2023 18:44, Bartosz Golaszewski wrote:
> > >> From: Shazad Hussain <quic_shazhuss@quicinc.com>
> > >>
> > >> Add support for the Global Clock Controller found in the QTI SA8775P
> > >> platforms.
> > >>
> > >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> > >> [Bartosz: made the driver ready for upstream]
> > >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > >> ---
> > > [...]
> > >
> >
> > As the driver didn't get to the list, I'll comment OOB.
> >
> > Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks).
> >
>
> Looks like it's impossible for this platform as the PCIe PIPE clocks
> have two parents.

That's the point, please check the history of other platforms. XO
becomes the 'off' state rather than being a separate parent.

On Mon, 9 Jan 2023 18:44:53 +0100, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> This adds basic support for the Qualcomm sa8775p platform and its reference
> board: sa8775p-ride. The dtsi contains basic SoC description required for
> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
> sa8775p-ride board. There are three new drivers required to boot the board:
> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
> to existing code. More support is coming up.
> 
> [...]

Applied, thanks!

[03/18] arm64: defconfig: enable the clock driver for Qualcomm SA8775P platforms
        commit: 1a87f7e5fa10b23633da03aed6b7c7e716457304

Best regards,

On Tue, Jan 10, 2023 at 5:26 PM Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Mon, Jan 09, 2023 at 06:45:03PM +0100, Bartosz Golaszewski wrote:
> [..]
> > +enum sa8775p_functions {
> > +     msm_mux_gpio,
> > +     msm_mux_atest_char,
> > +     msm_mux_atest_char0,
> > +     msm_mux_atest_char1,
> > +     msm_mux_atest_char2,
> > +     msm_mux_atest_char3,
> > +     msm_mux_atest_usb2,
> > +     msm_mux_atest_usb20,
> > +     msm_mux_atest_usb21,
> > +     msm_mux_atest_usb22,
> > +     msm_mux_atest_usb23,
>
> Please squash these to a single msm_mux_atest.

How about staying consistent with the sc8280xp which is the closest
platform to sa8775p and do a group for atest_char, a separate group
for atest_usb2...

>
> > +     msm_mux_audio_ref,
> > +     msm_mux_cam_mclk,
> > +     msm_mux_cci_async,
> > +     msm_mux_cci_i2c,
> > +     msm_mux_cci_timer0,
> > +     msm_mux_cci_timer1,
> > +     msm_mux_cci_timer2,
> > +     msm_mux_cci_timer3,
> > +     msm_mux_cci_timer4,
> > +     msm_mux_cci_timer5,
> > +     msm_mux_cci_timer6,
> > +     msm_mux_cci_timer7,
> > +     msm_mux_cci_timer8,
> > +     msm_mux_cci_timer9,
> > +     msm_mux_cri_trng,
> > +     msm_mux_cri_trng0,
> > +     msm_mux_cri_trng1,
> > +     msm_mux_dbg_out,
> > +     msm_mux_ddr_bist,
> > +     msm_mux_ddr_pxi0,
> > +     msm_mux_ddr_pxi1,
> > +     msm_mux_ddr_pxi2,
> > +     msm_mux_ddr_pxi3,
> > +     msm_mux_ddr_pxi4,
> > +     msm_mux_ddr_pxi5,
> > +     msm_mux_edp0_hot,
> > +     msm_mux_edp0_lcd,
> > +     msm_mux_edp1_hot,
> > +     msm_mux_edp1_lcd,
> > +     msm_mux_edp2_hot,
> > +     msm_mux_edp2_lcd,
> > +     msm_mux_edp3_hot,
> > +     msm_mux_edp3_lcd,
> > +     msm_mux_emac0_mcg0,
> > +     msm_mux_emac0_mcg1,
> > +     msm_mux_emac0_mcg2,
> > +     msm_mux_emac0_mcg3,
> > +     msm_mux_emac0_mdc,
> > +     msm_mux_emac0_mdio,
> > +     msm_mux_emac0_ptp,
>
> msm_mux_emac0
>
> > +     msm_mux_emac1_mcg0,
> > +     msm_mux_emac1_mcg1,
> > +     msm_mux_emac1_mcg2,
> > +     msm_mux_emac1_mcg3,
> > +     msm_mux_emac1_mdc,
> > +     msm_mux_emac1_mdio,
> > +     msm_mux_emac1_ptp,
>
> msm_mux_emac1
>

...leave these two here as is...

> > +     msm_mux_gcc_gp1,
> > +     msm_mux_gcc_gp2,
> > +     msm_mux_gcc_gp3,
> > +     msm_mux_gcc_gp4,
> > +     msm_mux_gcc_gp5,
> > +     msm_mux_hs0_mi2s,
> > +     msm_mux_hs1_mi2s,
> > +     msm_mux_hs2_mi2s,
> > +     msm_mux_ibi_i3c,
> > +     msm_mux_jitter_bist,
> > +     msm_mux_mdp0_vsync0,
> > +     msm_mux_mdp0_vsync1,
> > +     msm_mux_mdp0_vsync2,
> > +     msm_mux_mdp0_vsync3,
> > +     msm_mux_mdp0_vsync4,
> > +     msm_mux_mdp0_vsync5,
> > +     msm_mux_mdp0_vsync6,
> > +     msm_mux_mdp0_vsync7,
> > +     msm_mux_mdp0_vsync8,
> > +     msm_mux_mdp1_vsync0,
> > +     msm_mux_mdp1_vsync1,
> > +     msm_mux_mdp1_vsync2,
> > +     msm_mux_mdp1_vsync3,
> > +     msm_mux_mdp1_vsync4,
> > +     msm_mux_mdp1_vsync5,
> > +     msm_mux_mdp1_vsync6,
> > +     msm_mux_mdp1_vsync7,
> > +     msm_mux_mdp1_vsync8,
> > +     msm_mux_mdp_vsync,
> > +     msm_mux_mi2s1_data0,
> > +     msm_mux_mi2s1_data1,
> > +     msm_mux_mi2s1_sck,
> > +     msm_mux_mi2s1_ws,
> > +     msm_mux_mi2s2_data0,
> > +     msm_mux_mi2s2_data1,
> > +     msm_mux_mi2s2_sck,
> > +     msm_mux_mi2s2_ws,
> > +     msm_mux_mi2s_mclk0,
> > +     msm_mux_mi2s_mclk1,
> > +     msm_mux_pcie0_clkreq,
> > +     msm_mux_pcie1_clkreq,
> > +     msm_mux_phase_flag0,
> > +     msm_mux_phase_flag1,
> > +     msm_mux_phase_flag10,
> > +     msm_mux_phase_flag11,
> > +     msm_mux_phase_flag12,
> > +     msm_mux_phase_flag13,
> > +     msm_mux_phase_flag14,
> > +     msm_mux_phase_flag15,
> > +     msm_mux_phase_flag16,
> > +     msm_mux_phase_flag17,
> > +     msm_mux_phase_flag18,
> > +     msm_mux_phase_flag19,
> > +     msm_mux_phase_flag2,
> > +     msm_mux_phase_flag20,
> > +     msm_mux_phase_flag21,
> > +     msm_mux_phase_flag22,
> > +     msm_mux_phase_flag23,
> > +     msm_mux_phase_flag24,
> > +     msm_mux_phase_flag25,
> > +     msm_mux_phase_flag26,
> > +     msm_mux_phase_flag27,
> > +     msm_mux_phase_flag28,
> > +     msm_mux_phase_flag29,
> > +     msm_mux_phase_flag3,
> > +     msm_mux_phase_flag30,
> > +     msm_mux_phase_flag31,
> > +     msm_mux_phase_flag4,
> > +     msm_mux_phase_flag5,
> > +     msm_mux_phase_flag6,
> > +     msm_mux_phase_flag7,
> > +     msm_mux_phase_flag8,
> > +     msm_mux_phase_flag9,
>
> msm_mux_phase_flag
>

... change this one as you suggest...

> > +     msm_mux_pll_bist,
> > +     msm_mux_pll_clk,
> > +     msm_mux_prng_rosc0,
> > +     msm_mux_prng_rosc1,
> > +     msm_mux_prng_rosc2,
> > +     msm_mux_prng_rosc3,
> > +     msm_mux_qdss_cti,
> > +     msm_mux_qdss_gpio,
> > +     msm_mux_qdss_gpio0,
> > +     msm_mux_qdss_gpio1,
> > +     msm_mux_qdss_gpio10,
> > +     msm_mux_qdss_gpio11,
> > +     msm_mux_qdss_gpio12,
> > +     msm_mux_qdss_gpio13,
> > +     msm_mux_qdss_gpio14,
> > +     msm_mux_qdss_gpio15,
> > +     msm_mux_qdss_gpio2,
> > +     msm_mux_qdss_gpio3,
> > +     msm_mux_qdss_gpio4,
> > +     msm_mux_qdss_gpio5,
> > +     msm_mux_qdss_gpio6,
> > +     msm_mux_qdss_gpio7,
> > +     msm_mux_qdss_gpio8,
> > +     msm_mux_qdss_gpio9,
>
> msm_mux_qdss

... and have these as qdss_cti and qdss_gpio.

>
> > +     msm_mux_qup0_se0,
> > +     msm_mux_qup0_se1,
> > +     msm_mux_qup0_se2,
> > +     msm_mux_qup0_se3,
> > +     msm_mux_qup0_se4,
> > +     msm_mux_qup0_se5,
> > +     msm_mux_qup1_se0,
> > +     msm_mux_qup1_se1,
> > +     msm_mux_qup1_se2,
> > +     msm_mux_qup1_se3,
> > +     msm_mux_qup1_se4,
> > +     msm_mux_qup1_se5,
> > +     msm_mux_qup1_se6,
> > +     msm_mux_qup2_se0,
> > +     msm_mux_qup2_se1,
> > +     msm_mux_qup2_se2,
> > +     msm_mux_qup2_se3,
> > +     msm_mux_qup2_se4,
> > +     msm_mux_qup2_se5,
> > +     msm_mux_qup2_se6,
> > +     msm_mux_qup3_se0,
> > +     msm_mux_sail_top,
> > +     msm_mux_sailss_emac0,
> > +     msm_mux_sailss_ospi,
> > +     msm_mux_sgmii_phy,
> > +     msm_mux_tb_trig,
> > +     msm_mux_tgu_ch0,
> > +     msm_mux_tgu_ch1,
> > +     msm_mux_tgu_ch2,
> > +     msm_mux_tgu_ch3,
> > +     msm_mux_tgu_ch4,
> > +     msm_mux_tgu_ch5,
> > +     msm_mux_tsense_pwm1,
> > +     msm_mux_tsense_pwm2,
> > +     msm_mux_tsense_pwm3,
> > +     msm_mux_tsense_pwm4,
> > +     msm_mux_usb2phy_ac,
> > +     msm_mux_vsense_trigger,
> > +     msm_mux__,
> > +};
> > +
> [..]
> > +static const struct msm_pingroup sa8775p_groups[] = {
> > +     [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _),
> > +     [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _),
> > +     [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _),
> > +     [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _),
> > +     [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _),
> > +     [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _),
> > +     [6] = PINGROUP(6, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _, _),
>
> How is it possible to select the first or the second one of these
> functions when they are named the same?
>

I think Prasad and Yadu (the original authors of the driver) followed
the example from sc8280xp:

c0e4c71a9e7ce (Bjorn Andersson 2022-03-08 14:11:32 -0800 1804) [156] =
PINGROUP(156, qup6, emac0_ptp, emac0_ptp, _, _, _, _),

Do you remember what your original intention was? I also see that the
GPIOs repeat in the groups definitions:

 980 static const char * const emac0_ptp_groups[] = {
 981         "gpio130", "gpio130", "gpio131", "gpio131", "gpio156", "gpio156",
 982         "gpio157", "gpio157", "gpio158", "gpio158", "gpio159", "gpio159",
 983 };

[...]

Bart