| Message ID | 20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add IRQC support to RZ/G2UL SoC | expand |
On Wed, 21 Dec 2022 00:02:37 +0000, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for > which it has additional registers. > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string > and now that we have interrupt-names property the driver code parses the > interrupts based on names and for backward compatibility we fallback to > parse interrupts based on index. > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC > too and in future when the interrupt handler will be registered for > BUS_ERR_INT we will have to implement a new callback. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Since you're posting from a different address, please add a second SoB with your gmail address. > --- > v1 -> v2 > * New patch > --- > drivers/irqchip/irq-renesas-rzg2l.c | 80 ++++++++++++++++++++++++++--- > 1 file changed, 74 insertions(+), 6 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c > index 7918fe201218..5bdf0106ef51 100644 > --- a/drivers/irqchip/irq-renesas-rzg2l.c > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > @@ -299,19 +299,86 @@ static const struct irq_domain_ops rzg2l_irqc_domain_ops = { > .translate = irq_domain_translate_twocell, > }; > > -static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > - struct device_node *np) > +static int rzg2l_irqc_parse_interrupt_to_fwspec(struct rzg2l_irqc_priv *priv, > + struct device_node *np, > + unsigned int index, > + unsigned int fwspec_index) > { > struct of_phandle_args map; > + int ret; > + > + ret = of_irq_parse_one(np, index, &map); > + if (ret) > + return ret; > + > + of_phandle_args_to_fwspec(np, map.args, map.args_count, > + &priv->fwspec[fwspec_index]); > + > + return 0; > +} > + > +static int rzg2l_irqc_parse_interrupt_by_name_to_fwspec(struct rzg2l_irqc_priv *priv, > + struct device_node *np, > + char *irq_name, > + unsigned int fwspec_index) > +{ > + int index; > + > + index = of_property_match_string(np, "interrupt-names", irq_name); > + if (index < 0) > + return index; > + > + return rzg2l_irqc_parse_interrupt_to_fwspec(priv, np, index, fwspec_index); > +} > + > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */ > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv, > + struct device_node *np) > +{ > + struct property *pp; > unsigned int i; > int ret; > > + /* > + * first check if interrupt-names property exists if so parse them by name > + * or else parse them by index for backward compatibility. > + */ > + pp = of_find_property(np, "interrupt-names", NULL); > + if (pp) { > + char *irq_name; > + > + /* parse IRQ0-7 */ > + for (i = 0; i < IRQC_IRQ_COUNT; i++) { > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i); > + if (!irq_name) > + return -ENOMEM; > + > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i); Am I the only one that find it rather odd to construct a name from an index, only to get another index back? In any case, the string stuff could be moved into rzg2l_irqc_parse_interrupt_by_name_to_fwspec(). Which could really do with a name shortening)... rzg2l_irqc_name_to_fwspec? Same thing for the other function (rzg2l_irqc_index_to_fwspec). M.
On Wed, 21 Dec 2022 00:02:36 +0000, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > NMI interrupt is not an external interrupt as compared to the IRQ0-7 and > TINT0-31, this means we need to install the irq handler for NMI in the > IRQC driver and not include it as part of IRQ domain. > > This patch skips mapping NMI interrupt as part of the IRQ domain > hierarchy. Does it mean nobody can connect anything to it? Where is the handler you're mentioning for this NMI? > > Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1 -> v2 > * New patch > --- > drivers/irqchip/irq-renesas-rzg2l.c | 24 +++++++++++++----------- > 1 file changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c > index 25fd8ee66565..7918fe201218 100644 > --- a/drivers/irqchip/irq-renesas-rzg2l.c > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > @@ -23,7 +23,8 @@ > #define IRQC_IRQ_COUNT 8 > #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) > #define IRQC_TINT_COUNT 32 > -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) > + /* IRQ0-7 + TINT0-31 */ > +#define IRQC_NUM_HIERARCHY_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT - 1) > > #define ISCR 0x10 > #define IITSR 0x14 > @@ -58,7 +59,8 @@ > > struct rzg2l_irqc_priv { > void __iomem *base; > - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; > + /* IRQ0-7 + TINT0-31 will be part of hierarchy domain */ > + struct irq_fwspec fwspec[IRQC_NUM_HIERARCHY_IRQ]; > raw_spinlock_t lock; > }; > > @@ -99,7 +101,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) > raw_spin_lock(&priv->lock); > if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) > rzg2l_irq_eoi(d); > - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) > + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) > rzg2l_tint_eoi(d); > raw_spin_unlock(&priv->lock); > irq_chip_eoi_parent(d); > @@ -109,7 +111,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) > { > unsigned int hw_irq = irqd_to_hwirq(d); > > - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { > + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) { > struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); > u32 offset = hw_irq - IRQC_TINT_START; > u32 tssr_offset = TSSR_OFFSET(offset); > @@ -129,7 +131,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) > { > unsigned int hw_irq = irqd_to_hwirq(d); > > - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { > + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) { > struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); > unsigned long tint = (uintptr_t)d->chip_data; > u32 offset = hw_irq - IRQC_TINT_START; > @@ -228,7 +230,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) > > if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) > ret = rzg2l_irq_set_type(d, type); > - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) > + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) How about you define a "tint_hwirq()" helper that checks got the boundaries? Same thing for the other IRQ type. > ret = rzg2l_tint_set_edge(d, type); > if (ret) > return ret; > @@ -280,7 +282,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, > return -EINVAL; > } > > - if (hwirq > (IRQC_NUM_IRQ - 1)) > + if (!hwirq || hwirq > IRQC_NUM_HIERARCHY_IRQ) > return -EINVAL; > > ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, > @@ -288,7 +290,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, > if (ret) > return ret; > > - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); > + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq - 1]); > } > > static const struct irq_domain_ops rzg2l_irqc_domain_ops = { > @@ -304,12 +306,12 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > unsigned int i; > int ret; > > - for (i = 0; i < IRQC_NUM_IRQ; i++) { > + for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) { > ret = of_irq_parse_one(np, i, &map); > if (ret) > return ret; > of_phandle_args_to_fwspec(np, map.args, map.args_count, > - &priv->fwspec[i]); > + &priv->fwspec[i - 1]); Starting the loop at 1 really is non-idiomatic, and I'd rather see something like this: for (i = 0; i < IRQC_NUM_HIERARCHY_IRQ; i++) { ret = of_irq_parse_one(np, i + 1, &map); if (ret) return ret; of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]); } Thanks, M.
On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier <maz@kernel.org> wrote: > On Wed, 21 Dec 2022 00:02:37 +0000, > Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the > > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for > > which it has additional registers. > > > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string > > and now that we have interrupt-names property the driver code parses the > > interrupts based on names and for backward compatibility we fallback to > > parse interrupts based on index. > > > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC > > too and in future when the interrupt handler will be registered for > > BUS_ERR_INT we will have to implement a new callback. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */ > > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv, > > + struct device_node *np) > > +{ > > + struct property *pp; > > unsigned int i; > > int ret; > > > > + /* > > + * first check if interrupt-names property exists if so parse them by name > > + * or else parse them by index for backward compatibility. > > + */ > > + pp = of_find_property(np, "interrupt-names", NULL); > > + if (pp) { > > + char *irq_name; > > + > > + /* parse IRQ0-7 */ > > + for (i = 0; i < IRQC_IRQ_COUNT; i++) { > > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i); %u > > + if (!irq_name) > > + return -ENOMEM; > > + > > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i); > > Am I the only one that find it rather odd to construct a name from an > index, only to get another index back? The issue is that there are two number ranges ("irq%u" and "tint%u"), stored in a single interrupts property. An alternative solution would be to get rid of the "interrupt-names", and use two separate prefixed interrupts properties instead, like is common for e.g. gpios: "irq-interrupts" and "tint-interrupts". Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Wed, Dec 21, 2022 at 12:18 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier <maz@kernel.org> wrote: > > On Wed, 21 Dec 2022 00:02:37 +0000, > > Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the > > > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for > > > which it has additional registers. > > > > > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string > > > and now that we have interrupt-names property the driver code parses the > > > interrupts based on names and for backward compatibility we fallback to > > > parse interrupts based on index. > > > > > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC > > > too and in future when the interrupt handler will be registered for > > > BUS_ERR_INT we will have to implement a new callback. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */ > > > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv, > > > + struct device_node *np) > > > +{ > > > + struct property *pp; > > > unsigned int i; > > > int ret; > > > > > > + /* > > > + * first check if interrupt-names property exists if so parse them by name > > > + * or else parse them by index for backward compatibility. > > > + */ > > > + pp = of_find_property(np, "interrupt-names", NULL); > > > + if (pp) { > > > + char *irq_name; > > > + > > > + /* parse IRQ0-7 */ > > > + for (i = 0; i < IRQC_IRQ_COUNT; i++) { > > > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i); > > %u > Ok. > > > + if (!irq_name) > > > + return -ENOMEM; > > > + > > > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i); > > > > Am I the only one that find it rather odd to construct a name from an > > index, only to get another index back? > > The issue is that there are two number ranges ("irq%u" and "tint%u"), > stored in a single interrupts property. > > An alternative solution would be to get rid of the "interrupt-names", > and use two separate prefixed interrupts properties instead, like is > common for e.g. gpios: "irq-interrupts" and "tint-interrupts". > Maybe I will read all the interrupts based on index only for all the SoCs and we still add interrupt-names in dt bindings with the dt_binding check we can make sure all the interrupts for each SoC exist in the DT and the driver still reads them based on index. Does that sound good? Cheers, Prabhakar
Hi Marc, Geert, On Wed, Dec 21, 2022 at 10:31 AM Marc Zyngier <maz@kernel.org> wrote: > > On Wed, 21 Dec 2022 00:02:36 +0000, > Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > NMI interrupt is not an external interrupt as compared to the IRQ0-7 and > > TINT0-31, this means we need to install the irq handler for NMI in the > > IRQC driver and not include it as part of IRQ domain. > > > > This patch skips mapping NMI interrupt as part of the IRQ domain > > hierarchy. > > Does it mean nobody can connect anything to it? Where is the handler > you're mentioning for this NMI? > I got this clarified internally the NMI interrupt is an external interrupt just like the other IRQ0-7/TINT interrupts. I'll drop this patch in the next version. Cheers, Prabhakar
Hi Prabhakar, On Thu, Dec 22, 2022 at 12:50 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Wed, Dec 21, 2022 at 12:18 PM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: > > On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier <maz@kernel.org> wrote: > > > On Wed, 21 Dec 2022 00:02:37 +0000, > > > Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the > > > > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for > > > > which it has additional registers. > > > > > > > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string > > > > and now that we have interrupt-names property the driver code parses the > > > > interrupts based on names and for backward compatibility we fallback to > > > > parse interrupts based on index. > > > > > > > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC > > > > too and in future when the interrupt handler will be registered for > > > > BUS_ERR_INT we will have to implement a new callback. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */ > > > > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv, > > > > + struct device_node *np) > > > > +{ > > > > + struct property *pp; > > > > unsigned int i; > > > > int ret; > > > > > > > > + /* > > > > + * first check if interrupt-names property exists if so parse them by name > > > > + * or else parse them by index for backward compatibility. > > > > + */ > > > > + pp = of_find_property(np, "interrupt-names", NULL); > > > > + if (pp) { > > > > + char *irq_name; > > > > + > > > > + /* parse IRQ0-7 */ > > > > + for (i = 0; i < IRQC_IRQ_COUNT; i++) { > > > > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i); > > > > %u > > > Ok. > > > > > + if (!irq_name) > > > > + return -ENOMEM; > > > > + > > > > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i); > > > > > > Am I the only one that find it rather odd to construct a name from an > > > index, only to get another index back? > > > > The issue is that there are two number ranges ("irq%u" and "tint%u"), > > stored in a single interrupts property. > > > > An alternative solution would be to get rid of the "interrupt-names", > > and use two separate prefixed interrupts properties instead, like is > > common for e.g. gpios: "irq-interrupts" and "tint-interrupts". > > > Maybe I will read all the interrupts based on index only for all the > SoCs and we still add interrupt-names in dt bindings with the > dt_binding check we can make sure all the interrupts for each SoC > exist in the DT and the driver still reads them based on index. Does > that sound good? Sure, sounds fine. You can postpone parsing interrupt-names in the driver (until a new SoC arrives that uses a different number of IRQ or TINT interrupts). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Prabhakar, On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and > ETH1 respectively. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > @@ -6,6 +6,7 @@ > */ > > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> > #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > > / { > @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 { > compatible = "ethernet-phy-id0022.1640", > "ethernet-phy-ieee802.3-c22"; > reg = <7>; > + interrupt-parent = <&irqc>; Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have the irqc node yet, so I cannot take this as-is. > + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; > rxc-skew-psec = <2400>; > txc-skew-psec = <2400>; > rxdv-skew-psec = <0>; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Tue, Dec 27, 2022 at 1:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and > > ETH1 respectively. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > > @@ -6,6 +6,7 @@ > > */ > > > > #include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> > > #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > > > > / { > > @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 { > > compatible = "ethernet-phy-id0022.1640", > > "ethernet-phy-ieee802.3-c22"; > > reg = <7>; > > + interrupt-parent = <&irqc>; > > Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have > the irqc node yet, so I cannot take this as-is. > Agreed, is it OK if we temporarily add the (above+below) properties in the boards DTS and once we have full fledged support for RZ/Five we move it back to the SoM DTSi (as done in this patch)? Cheers, Prabhakar > > + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; > > rxc-skew-psec = <2400>; > > txc-skew-psec = <2400>; > > rxdv-skew-psec = <0>; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, This patch series does the following: * Adds IRQC support to the RZ/G2UL SoC. * Drops mapping NMI interrupt as part of IRQ domain * Parses interrupts based in interrupt-names * Includes a fix for pinctrl driver when using GPIO pins as interrupts * Adds PHY interrupt support for ETH{0/1} v1->v2 * Updated binding doc * Dropped mapping NMI interrupt as part of IRQ domain * Fixed review comments pointed by Geert * Added support to parse interrupts by name * Added compile time checks for gpio config arrays RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (9): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC dt-bindings: interrupt-controller: irqc-rzg2l: Drop RZG2L_NMI macro irqchip: irq-renesas-rzg2l: Skip mapping NMI interrupt as part of hierarchy domain irqchip: irq-renesas-rzg2l: Add support for RZ/G2UL SoC pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks arm64: dts: renesas: r9a07g043u: Add IRQC node arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} .../renesas,rzg2l-irqc.yaml | 240 +++++++++++++----- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 + arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++++ .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +- drivers/irqchip/irq-renesas-rzg2l.c | 102 ++++++-- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +- .../interrupt-controller/irqc-rzg2l.h | 3 - 7 files changed, 366 insertions(+), 89 deletions(-)