| Message ID | 20221124135646.1952727-1-abel.vesa@linaro.org |
|---|---|
| Headers | show |
| Series | arm64: dts: Add base device tree files for SM8550 | expand |
On 24.11.2022 14:56, Abel Vesa wrote: > Add base dtsi for SM8550 SoC and includes base description of > CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved > memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, > interconnect, thermal sensor, cpu cooling maps and SMMU nodes > which helps boot to shell with console on boards with this SoC. > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- [...] > + reserved_memory: reserved-memory { > + ranges; > + > + #address-cells = <2>; > + #size-cells = <2>; #address-cells = <2>; #size-cells = <2>; ranges; > + > + hyp_mem: hyp-region@80000000 { > + reg = <0x0 0x80000000 0x0 0xa00000>; > + no-map; > + }; > + > + > + sdhc_2: mmc@8804000 { > + compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x08804000 0x0 0x1000>; > + > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "core", "xo"; > + iommus = <&apps_smmu 0x540 0x0>; > + qcom,dll-config = <0x0007642c>; > + qcom,ddr-config = <0x80040868>; > + power-domains = <&rpmhpd SM8550_CX>; > + operating-points-v2 = <&sdhc2_opp_table>; > + > + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; > + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > + > + /* Forbid SDR104/SDR50 - broken hw! */ > + sdhci-caps-mask = <0x3 0x0>; > + > + status = "disabled"; > + 8450 needs `dma-coherent` there - I don't have any downstream for 8550 to cross reference, could you check if this is the case here too? > + sdhc2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-19200000 { > + opp-hz = /bits/ 64 <19200000>; > + required-opps = <&rpmhpd_opp_min_svs>; > + }; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-202000000 { > + opp-hz = /bits/ 64 <202000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm8550-pdc", "qcom,pdc"; > + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; > + qcom,pdc-ranges = <0 480 94>, <94 609 31>, > + <125 63 1>, <126 716 12>, > + <138 251 5>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + tsens0: thermal-sensor@c271000 { > + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c271000 0 0x1000>, /* TM */ > + <0 0x0c222000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > + tsens1: thermal-sensor@c272000 { > + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c272000 0 0x1000>, /* TM */ > + <0 0x0c223000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > + tsens2: thermal-sensor@c273000 { > + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c273000 0 0x1000>, /* TM */ > + <0 0x0c224000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > + aoss_qmp: power-controller@c300000 { > + compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; > + reg = <0 0x0c300000 0 0x400>; > + interrupt-parent = <&ipcc>; > + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + #clock-cells = <0>; > + }; > + > + sram@c3f0000 { > + compatible = "qcom,rpmh-stats"; > + reg = <0x0 0x0c3f0000 0x0 0x400>; > + }; > + > + spmi_bus: spmi@c400000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0x0c400000 0x0 0x3000>, > + <0x0 0x0c500000 0x0 0x4000000>, > + <0x0 0x0c440000 0x0 0x80000>, > + <0x0 0x0c4c0000 0x0 0x20000>, > + <0x0 0x0c42d000 0x0 0x4000>; You use 0 and 0x0 inconsistently in reg. I propose to use 0 everywhere. > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + qcom,ee = <0>; > + qcom,channel = <0>; > + qcom,bus-id = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + }; > + [...] > + > + pmu@24091000 { > + compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; > + reg = <0x0 0x24091000 0x0 0x1000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; > + > + operating-points-v2 = <&llcc_bwmon_opp_table>; > + > + llcc_bwmon_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-0 { > + opp-peak-kBps = <2086000>; > + }; Please insert a newline after each node. > + opp-1 { > + opp-peak-kBps = <2929000>; > + }; > + opp-2 { > + opp-peak-kBps = <5931000>; > + }; > + opp-3 { > + opp-peak-kBps = <6515000>; > + }; > + opp-4 { > + opp-peak-kBps = <7980000>; > + }; > + opp-5 { > + opp-peak-kBps = <10437000>; > + }; > + opp-6 { > + opp-peak-kBps = <12157000>; > + }; > + opp-7 { > + opp-peak-kBps = <14060000>; > + }; > + opp-8 { > + opp-peak-kBps = <16113000>; > + }; > + }; > + }; > + > + pmu@240b6400 { > + compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; > + reg = <0x0 0x240b6400 0x0 0x600>; > + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; > + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; > + > + operating-points-v2 = <&cpu_bwmon_opp_table>; > + > + cpu_bwmon_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-0 { > + opp-peak-kBps = <4577000>; > + }; And here. > + opp-1 { > + opp-peak-kBps = <7110000>; > + }; > + opp-2 { > + opp-peak-kBps = <9155000>; > + }; > + opp-3 { > + opp-peak-kBps = <12298000>; > + }; > + opp-4 { > + opp-peak-kBps = <14236000>; > + }; > + opp-5 { > + opp-peak-kBps = <16265000>; > + }; > + }; > + }; > + The rest looks good! Konrad
On 24.11.2022 14:56, Abel Vesa wrote: > Add dts file for Qualcomm MTP platform which uses SM8550 SoC. > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > > Changes since v1: > * renamed all pm8550*-rpmh-regulators regulators-* > * moved the status property in the proper place > * removed the card-det-pins envelope node > * moved sdc2-default-state to the dtsi file > > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 404 ++++++++++++++++++++++++ > 2 files changed, 405 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm8550-mtp.dts > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index afe496a93f94..b447b3082c84 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -169,3 +169,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb > diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > new file mode 100644 > index 000000000000..b0bcabecd60e > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > @@ -0,0 +1,404 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Linaro Limited > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> > +#include "sm8550.dtsi" > +#include "pm8010.dtsi" > +#include "pm8550.dtsi" > +#include "pm8550b.dtsi" > +#include "pm8550ve.dtsi" > +#include "pm8550vs.dtsi" > +#include "pmk8550.dtsi" > +#include "pmr735d.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. SM8550 MTP"; > + compatible = "qcom,sm8550-mtp", "qcom,sm8550"; > + > + aliases { > + serial0 = &uart7; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + vph_pwr: vph-pwr-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vph_pwr"; > + regulator-min-microvolt = <3700000>; > + regulator-max-microvolt = <3700000>; > + > + regulator-always-on; > + regulator-boot-on; > + }; > +}; > + > +&apps_rsc { > + regulators-0 { > + compatible = "qcom,pm8550-rpmh-regulators"; > + qcom,pmic-id = "b"; > + > + vdd-bob1-supply = <&vph_pwr>; > + vdd-bob2-supply = <&vph_pwr>; > + vdd-l2-l13-l14-supply = <&vreg_bob1>; > + vdd-l3-supply = <&vreg_s4g_1p3>; > + vdd-l6-l16-supply = <&vreg_bob1>; > + vdd-l6-l7-supply = <&vreg_bob1>; > + vdd-l8-l9-supply = <&vreg_bob1>; > + vdd-l11-supply = <&vreg_s4g_1p3>; > + vdd-l12-supply = <&vreg_s6g_1p8>; > + vdd-l15-supply = <&vreg_s6g_1p8>; > + vdd-l17-supply = <&vreg_bob2>; > + > + vreg_bob1: bob1 { > + regulator-name = "vreg_bob1"; > + regulator-min-microvolt = <3296000>; > + regulator-max-microvolt = <3960000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_bob2: bob2 { > + regulator-name = "vreg_bob2"; > + regulator-min-microvolt = <2720000>; > + regulator-max-microvolt = <3960000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l1b_1p8: ldo1 { > + regulator-name = "vreg_l1b_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l2b_3p0: ldo2 { > + regulator-name = "vreg_l2b_3p0"; > + regulator-min-microvolt = <3008000>; > + regulator-max-microvolt = <3008000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l5b_3p1: ldo5 { > + regulator-name = "vreg_l5b_3p1"; > + regulator-min-microvolt = <3104000>; > + regulator-max-microvolt = <3104000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l6b_1p8: ldo6 { > + regulator-name = "vreg_l6b_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3008000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l7b_1p8: ldo7 { > + regulator-name = "vreg_l7b_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3008000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l8b_1p8: ldo8 { > + regulator-name = "vreg_l8b_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3008000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l9b_2p9: ldo9 { > + regulator-name = "vreg_l9b_2p9"; > + regulator-min-microvolt = <2960000>; > + regulator-max-microvolt = <3008000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l11b_1p2: ldo11 { > + regulator-name = "vreg_l11b_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1504000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l12b_1p8: ldo12 { > + regulator-name = "vreg_l12b_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l13b_3p0: ldo13 { > + regulator-name = "vreg_l13b_3p0"; > + regulator-min-microvolt = <3000000>; > + regulator-max-microvolt = <3000000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l14b_3p2: ldo14 { > + regulator-name = "vreg_l14b_3p2"; > + regulator-min-microvolt = <3200000>; > + regulator-max-microvolt = <3200000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l15b_1p8: ldo15 { > + regulator-name = "vreg_l15b_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l16b_2p8: ldo16 { > + regulator-name = "vreg_l16b_2p8"; > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l17b_2p5: ldo17 { > + regulator-name = "vreg_l17b_2p5"; > + regulator-min-microvolt = <2504000>; > + regulator-max-microvolt = <2504000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + }; > + > + regulators-1 { > + compatible = "qcom,pm8550vs-rpmh-regulators"; > + qcom,pmic-id = "c"; > + > + vdd-l3-supply = <&vreg_s4e_0p9>; > + > + vreg_l3c_0p91: ldo3 { > + regulator-name = "vreg_l3c_0p9"; > + regulator-min-microvolt = <880000>; > + regulator-max-microvolt = <912000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + }; > + > + regulators-2 { > + compatible = "qcom,pm8550vs-rpmh-regulators"; > + qcom,pmic-id = "d"; > + > + vdd-l1-supply = <&vreg_s4e_0p9>; > + > + vreg_l1d_0p88: ldo1 { > + regulator-name = "vreg_l1d_0p88"; > + regulator-min-microvolt = <880000>; > + regulator-max-microvolt = <920000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + }; > + > + regulators-3 { > + compatible = "qcom,pm8550vs-rpmh-regulators"; > + qcom,pmic-id = "e"; > + > + vdd-l1-supply = <&vreg_s4e_0p9>; > + vdd-l2-supply = <&vreg_s4e_0p9>; > + vdd-l3-supply = <&vreg_s4g_1p3>; > + vdd-s4-supply = <&vph_pwr>; > + vdd-s5-supply = <&vph_pwr>; > + > + vreg_s4e_0p9: smps4 { > + regulator-name = "vreg_s4e_0p9"; > + regulator-min-microvolt = <904000>; > + regulator-max-microvolt = <984000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_s5e_1p1: smps5 { > + regulator-name = "vreg_s5e_1p1"; > + regulator-min-microvolt = <1080000>; > + regulator-max-microvolt = <1120000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l1e_0p88: ldo1 { > + regulator-name = "vreg_l1e_0p88"; > + regulator-min-microvolt = <880000>; > + regulator-max-microvolt = <880000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l2e_0p9: ldo2 { > + regulator-name = "vreg_l2e_0p9"; > + regulator-min-microvolt = <904000>; > + regulator-max-microvolt = <970000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l3e_1p2: ldo3 { > + regulator-name = "vreg_l3e_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + }; > + > + regulators-4 { > + compatible = "qcom,pm8550ve-rpmh-regulators"; > + qcom,pmic-id = "f"; > + > + vdd-l1-supply = <&vreg_s4e_0p9>; > + vdd-l2-supply = <&vreg_s4e_0p9>; > + vdd-l3-supply = <&vreg_s4e_0p9>; > + vdd-s4-supply = <&vph_pwr>; > + > + vreg_s4f_0p5: smps4 { > + regulator-name = "vreg_s4f_0p5"; > + regulator-min-microvolt = <500000>; > + regulator-max-microvolt = <700000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l1f_0p9: ldo1 { > + regulator-name = "vreg_l1f_0p9"; > + regulator-min-microvolt = <912000>; > + regulator-max-microvolt = <912000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l2f_0p88: ldo2 { > + regulator-name = "vreg_l2f_0p88"; > + regulator-min-microvolt = <880000>; > + regulator-max-microvolt = <912000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l3f_0p91: ldo3 { > + regulator-name = "vreg_l3f_0p91"; > + regulator-min-microvolt = <880000>; > + regulator-max-microvolt = <912000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + }; > + > + regulators-5 { > + compatible = "qcom,pm8550vs-rpmh-regulators"; > + qcom,pmic-id = "g"; > + > + vdd-l1-supply = <&vreg_s4g_1p3>; > + vdd-l2-supply = <&vreg_s4g_1p3>; > + vdd-l3-supply = <&vreg_s4g_1p3>; > + vdd-s1-supply = <&vph_pwr>; > + vdd-s2-supply = <&vph_pwr>; > + vdd-s3-supply = <&vph_pwr>; > + vdd-s4-supply = <&vph_pwr>; > + vdd-s5-supply = <&vph_pwr>; > + vdd-s6-supply = <&vph_pwr>; > + > + vreg_s1g_1p2: smps1 { > + regulator-name = "vreg_s1g_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1300000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_s2g_0p8: smps2 { > + regulator-name = "vreg_s2g_0p8"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1000000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_s3g_0p7: smps3 { > + regulator-name = "vreg_s3g_0p7"; > + regulator-min-microvolt = <300000>; > + regulator-max-microvolt = <1004000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_s4g_1p3: smps4 { > + regulator-name = "vreg_s4g_1p3"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1352000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_s5g_0p8: smps5 { > + regulator-name = "vreg_s5g_0p8"; > + regulator-min-microvolt = <500000>; > + regulator-max-microvolt = <1004000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_s6g_1p8: smps6 { > + regulator-name = "vreg_s6g_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <2000000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l1g_1p2: ldo1 { > + regulator-name = "vreg_l1g_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l2g_1p2: ldo2 { > + regulator-name = "vreg_l2g_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l3g_1p2: ldo3 { > + regulator-name = "vreg_l3g_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + }; > +}; > + > +&pm8550_gpios { > + sdc2_card_det_n: sdc2-card-det-state { > + pins = "gpio12"; > + function = "normal"; > + input-enable; > + output-disable; > + bias-pull-up; > + power-source = <1>; /* 1.8 V */ > + }; > +}; > + > +&qupv3_id_0 { > + status = "okay"; > +}; > + > +&sdhc_2 { > + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; > + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; > + vmmc-supply = <&vreg_l9b_2p9>; > + vqmmc-supply = <&vreg_l8b_1p8>; > + bus-width = <4>; > + no-sdio; > + no-emmc; > + status = "okay"; > +}; > + > +&sleep_clk { > + clock-frequency = <32000>; > +}; > + > +&tlmm { > + gpio-reserved-ranges = <32 8>; > +}; > + > +&uart7 { > + status = "okay"; > +}; > + > +&xo_board { > + clock-frequency = <76800000>; > +};
Hi, On 11/24/2022 7:26 PM, Abel Vesa wrote: > Add base dtsi for SM8550 SoC and includes base description of > CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved > memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, > interconnect, thermal sensor, cpu cooling maps and SMMU nodes > which helps boot to shell with console on boards with this SoC. > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- <snip>... > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2. Thanks, Sai
On 24.11.2022 16:39, Sai Prakash Ranjan wrote: > Hi, > > On 11/24/2022 7:26 PM, Abel Vesa wrote: >> Add base dtsi for SM8550 SoC and includes base description of >> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved >> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, >> interconnect, thermal sensor, cpu cooling maps and SMMU nodes >> which helps boot to shell with console on boards with this SoC. >> >> Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> --- > > <snip>... > >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > > This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2. Does non-CrOS 8550 FW allow Linux to boot in EL2? Konrad > > Thanks, > Sai
On 11/24/2022 9:10 PM, Konrad Dybcio wrote: > > > On 24.11.2022 16:39, Sai Prakash Ranjan wrote: >> Hi, >> >> On 11/24/2022 7:26 PM, Abel Vesa wrote: >>> Add base dtsi for SM8550 SoC and includes base description of >>> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved >>> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, >>> interconnect, thermal sensor, cpu cooling maps and SMMU nodes >>> which helps boot to shell with console on boards with this SoC. >>> >>> Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> >>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >> >> <snip>... >> >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >> >> This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2. > Does non-CrOS 8550 FW allow Linux to boot in EL2? > Sadly no, which is why this entry always gets wrong downstream. Thanks, Sai