[00/12] PXA168 clock fixes

Hello,

I have been working on bringing the PXA168 support in the kernel up to
snuff. I found several mistakes in the clock muxing, and began work on
getting the SDHC controllers hooked up properly. I've been testing these
changes on a device that uses the PXA168 (Chumby 8).

I'm a little unsure if I'm following the correct approach in the last
two patches, and would definitely appreciate some feedback if there is
a more appropriate way to handle this situation where two peripherals
share a clock enable in a single register. In particular, I wasn't sure
if creating the shared clocks without a parent at all would be okay:

[11/12] dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks
[12/12] clk: mmp: pxa168: control shared SDH bits with separate clock

I'm aware that checkpatch warns about the long lines, but I was unsure
if that actually mattered given that the existing file also has the
warnings.

I plan on continuing to work on additional PXA168 fixes over time.

Thanks,
Doug

Quoting Doug Brown (2022-06-12 12:29:26)
> In preparation for adding additional peripherals over time, this commit
> adds a bunch of extra APBC_* defines based on information from the
> datasheet. It also reorganizes the list of defines to be ordered
> sequentially by address (grouped by type).
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:27)
> These two clocks had multipliers and dividers that didn't match their
> names. A subsequent commit goes through all of the existing peripherals
> and ensure the correct clocks are being used everywhere.
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:29)
> This commit adds three new clocks that previously didn't exist, but are
> needed in order to match the clock parenting as described in the PXA168
> datasheet.
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:30)
> While working on this series of patches, checkpatch recommended that
> an extra const should be added to the mux parent arrays.
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:31)
> The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't
> match the information provided by the PXA168 datasheet:
> 
> - The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first
>   mux option was being calculated as 117 MHz, confirmed on hardware to
>   be incorrect.
> 
> - The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz
>   and 52 MHz were swapped. 78 MHz wasn't listed as an option.
> 
> - The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being
>   calculated as 312 MHz or 52 MHz.
> 
> - The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being
>   calculated as 312 MHz or 52 MHz.
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:32)
> The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled
> in the code, but the PXA168 datasheet shows that they are indeed muxed:
> 
> - TWSI can be 31.2 MHz or 62.4 MHz
> - KPC can be 32 kHz, 16 kHz, or 26 MHz
> - PWM can be 13 MHz or 32 kHz
> - DFC can be 156 MHz or 78 MHz
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:33)
> According to the datasheet, only bit 0 of APBC_GPIO should be controlled
> for the clock enable. Bit 1 is marked as reserved (always write 0).
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:35)
> The PXA168 has four SDHC peripherals. This commit adds the last two.
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next

Quoting Doug Brown (2022-06-12 12:29:37)
> The PXA168 has a peculiar setup with the AXI clock enable control for
> the SDHC controllers. The bits in the SDH0 register control the AXI
> clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2
> register control both SDH2 and SDH3. This is modeled with two new
> parentless clocks that control the shared bits.
> 
> Previously, SDH0 had to be enabled in order for SDH1 to be used, and
> when SDH1 was enabled, unused bits in the SDH1 register were being
> controlled. This fixes those issues. A future commit will add support
> for these new shared clocks to be enabled by the PXA168 SDHC driver.
> 
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next