mbox series

[v3,0/5] Add interconnect support for SM6350

Message ID 20220525144404.200390-1-luca.weiss@fairphone.com
Headers show
Series Add interconnect support for SM6350 | expand

Message

Luca Weiss May 25, 2022, 2:43 p.m. UTC 
This series adds interconnect support for the various NoCs found on
sm6350.

A more special modification is allowing child NoC devices, like done for
rpm-based qcm2290 which was already merged, but now for rpmh-based
interconnect.

See also downstream dts:
https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-11.0.0_r0.81/qcom/lagoon-bus.dtsi

Luca Weiss (5):
  interconnect: qcom: icc-rpmh: Support child NoC device probe
  dt-bindings: interconnect: qcom: Split out rpmh-common bindings
  dt-bindings: interconnect: Add Qualcomm SM6350 NoC support
  interconnect: qcom: Add SM6350 driver support
  arm64: dts: qcom: sm6350: Add interconnect support

 .../interconnect/qcom,rpmh-common.yaml        |  43 ++
 .../bindings/interconnect/qcom,rpmh.yaml      |  22 +-
 .../interconnect/qcom,sm6350-rpmh.yaml        |  82 +++
 arch/arm64/boot/dts/qcom/sm6350.dtsi          | 109 ++++
 drivers/interconnect/qcom/Kconfig             |   9 +
 drivers/interconnect/qcom/Makefile            |   2 +
 drivers/interconnect/qcom/icc-rpmh.c          |   4 +
 drivers/interconnect/qcom/sm6350.c            | 493 ++++++++++++++++++
 drivers/interconnect/qcom/sm6350.h            | 139 +++++
 .../dt-bindings/interconnect/qcom,sm6350.h    | 148 ++++++
 10 files changed, 1034 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
 create mode 100644 drivers/interconnect/qcom/sm6350.c
 create mode 100644 drivers/interconnect/qcom/sm6350.h
 create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h

Comments

Luca Weiss July 15, 2022, 1:34 p.m. UTC | #1 
Hi all,

On Wed May 25, 2022 at 4:43 PM CEST, Luca Weiss wrote:
> This series adds interconnect support for the various NoCs found on
> sm6350.
>
> A more special modification is allowing child NoC devices, like done for
> rpm-based qcm2290 which was already merged, but now for rpmh-based
> interconnect.

any feedback on the two interconnect patches and the dts patch?
Georgi? Bjorn?

Thanks Krzysztof for the dt-binding review!

Regards
Luca

>
> See also downstream dts:
> https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-11.0.0_r0.81/qcom/lagoon-bus.dtsi
>
> Luca Weiss (5):
>   interconnect: qcom: icc-rpmh: Support child NoC device probe
>   dt-bindings: interconnect: qcom: Split out rpmh-common bindings
>   dt-bindings: interconnect: Add Qualcomm SM6350 NoC support
>   interconnect: qcom: Add SM6350 driver support
>   arm64: dts: qcom: sm6350: Add interconnect support
>
>  .../interconnect/qcom,rpmh-common.yaml        |  43 ++
>  .../bindings/interconnect/qcom,rpmh.yaml      |  22 +-
>  .../interconnect/qcom,sm6350-rpmh.yaml        |  82 +++
>  arch/arm64/boot/dts/qcom/sm6350.dtsi          | 109 ++++
>  drivers/interconnect/qcom/Kconfig             |   9 +
>  drivers/interconnect/qcom/Makefile            |   2 +
>  drivers/interconnect/qcom/icc-rpmh.c          |   4 +
>  drivers/interconnect/qcom/sm6350.c            | 493 ++++++++++++++++++
>  drivers/interconnect/qcom/sm6350.h            | 139 +++++
>  .../dt-bindings/interconnect/qcom,sm6350.h    | 148 ++++++
>  10 files changed, 1034 insertions(+), 17 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
>  create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
>  create mode 100644 drivers/interconnect/qcom/sm6350.c
>  create mode 100644 drivers/interconnect/qcom/sm6350.h
>  create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h
>
> -- 
> 2.36.1
Georgi Djakov July 18, 2022, 7:15 a.m. UTC | #2 
On 15.07.22 16:34, Luca Weiss wrote:
> Hi all,
> 
> On Wed May 25, 2022 at 4:43 PM CEST, Luca Weiss wrote:
>> This series adds interconnect support for the various NoCs found on
>> sm6350.
>>
>> A more special modification is allowing child NoC devices, like done for
>> rpm-based qcm2290 which was already merged, but now for rpmh-based
>> interconnect.
> 
> any feedback on the two interconnect patches and the dts patch?
> Georgi? Bjorn?

I merged the interconnect patches.

Thanks,
Georgi
Georgi Djakov July 18, 2022, 7:58 a.m. UTC | #3 
On 25.05.22 17:44, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * none
> 
>   arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++
>   1 file changed, 109 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index fb1a0f662575..119073f19285 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1,11 +1,13 @@
>   // SPDX-License-Identifier: BSD-3-Clause
>   /*
>    * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> + * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
>    */
>   
>   #include <dt-bindings/clock/qcom,gcc-sm6350.h>
>   #include <dt-bindings/clock/qcom,rpmh.h>
>   #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,sm6350.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/mailbox/qcom-ipcc.h>
>   #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -539,6 +541,10 @@ i2c0: i2c@880000 {
>   				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> +						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>   				status = "disabled";
>   			};
>   
> @@ -552,6 +558,10 @@ i2c2: i2c@888000 {
>   				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> +						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>   				status = "disabled";
>   			};
>   		};
> @@ -578,6 +588,10 @@ i2c6: i2c@980000 {
>   				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>   				status = "disabled";
>   			};
>   
> @@ -591,6 +605,10 @@ i2c7: i2c@984000 {
>   				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>   				status = "disabled";
>   			};
>   
> @@ -604,6 +622,10 @@ i2c8: i2c@988000 {
>   				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>   				status = "disabled";
>   			};
>   
> @@ -615,6 +637,9 @@ uart9: serial@98c000 {
>   				pinctrl-names = "default";
>   				pinctrl-0 = <&qup_uart9_default>;
>   				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
> +				interconnect-names = "qup-core", "qup-config";
>   				status = "disabled";
>   			};
>   
> @@ -628,11 +653,62 @@ i2c10: i2c@990000 {
>   				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
>   				#address-cells = <1>;
>   				#size-cells = <0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";
>   				status = "disabled";
>   			};
>   
>   		};
>   
> +		config_noc: interconnect@1500000 {
> +			compatible = "qcom,sm6350-config-noc";
> +			reg = <0 0x01500000 0 0x28000>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		system_noc: interconnect@1620000 {
> +			compatible = "qcom,sm6350-system-noc";
> +			reg = <0 0x01620000 0 0x17080>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +
> +			clk_virt: interconnect-clk-virt {
> +				compatible = "qcom,sm6350-clk-virt";
> +				#interconnect-cells = <2>;
> +				qcom,bcm-voters = <&apps_bcm_voter>;
> +			};
> +		};
> +
> +		aggre1_noc: interconnect@16e0000 {
> +			compatible = "qcom,sm6350-aggre1-noc";
> +			reg = <0 0x016e0000 0 0x15080>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre2_noc: interconnect@1700000 {
> +			compatible = "qcom,sm6350-aggre2-noc";
> +			reg = <0 0x01700000 0 0x1f880>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +
> +			compute_noc: interconnect-compute-noc {
> +				compatible = "qcom,sm6350-compute-noc";
> +				#interconnect-cells = <2>;
> +				qcom,bcm-voters = <&apps_bcm_voter>;
> +			};
> +		};
> +
> +		mmss_noc: interconnect@1740000 {
> +			compatible = "qcom,sm6350-mmss-noc";
> +			reg = <0 0x01740000 0 0x1c100>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>   		ufs_mem_hc: ufs@1d84000 {
>   			compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
>   				     "jedec,ufs-2.0";
> @@ -933,6 +1009,10 @@ sdhc_2: sdhci@8804000 {
>   				 <&gcc GCC_SDCC2_APPS_CLK>,
>   				 <&rpmhcc RPMH_CXO_CLK>;
>   			clock-names = "iface", "core", "xo";
> +			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> +					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> +			interconnect-names = "sdhc-ddr", "cpu-sdhc";
> +
>   			qcom,dll-config = <0x0007642c>;
>   			qcom,ddr-config = <0x80040868>;
>   			power-domains = <&rpmhpd 0>;
> @@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table {
>   				opp-100000000 {
>   					opp-hz = /bits/ 64 <100000000>;
>   					required-opps = <&rpmhpd_opp_svs_l1>;
> +					opp-peak-kBps = <790000 131000>;
> +					opp-avg-kBps = <50000 50000>;
>   				};
>   
>   				opp-202000000 {
>   					opp-hz = /bits/ 64 <202000000>;
>   					required-opps = <&rpmhpd_opp_nom>;
> +					opp-peak-kBps = <3190000 294000>;
> +					opp-avg-kBps = <261438 300000>;

Just wondering where do these values come from? Are they from the downstream DT?
The rest looks good to me.

Thanks,
Georgi

>   				};
>   			};
>   		};
> @@ -1017,12 +1101,33 @@ dp_phy: dp-phy@88ea200 {
>   			};
>   		};
>   
> +		dc_noc: interconnect@9160000 {
> +			compatible = "qcom,sm6350-dc-noc";
> +			reg = <0 0x09160000 0 0x3200>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>   		system-cache-controller@9200000 {
>   			compatible = "qcom,sm6350-llcc";
>   			reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
>   			reg-names = "llcc_base", "llcc_broadcast_base";
>   		};
>   
> +		gem_noc: interconnect@9680000 {
> +			compatible = "qcom,sm6350-gem-noc";
> +			reg = <0 0x09680000 0 0x3e200>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		npu_noc: interconnect@9990000 {
> +			compatible = "qcom,sm6350-npu-noc";
> +			reg = <0 0x09990000 0 0x1600>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>   		usb_1: usb@a6f8800 {
>   			compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
>   			reg = <0 0x0a6f8800 0 0x400>;
> @@ -1051,6 +1156,10 @@ usb_1: usb@a6f8800 {
>   
>   			resets = <&gcc GCC_USB30_PRIM_BCR>;
>   
> +			interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
> +					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
> +			interconnect-names = "usb-ddr", "apps-usb";
> +
>   			usb_1_dwc3: usb@a600000 {
>   				compatible = "snps,dwc3";
>   				reg = <0 0x0a600000 0 0xcd00>;
Luca Weiss July 18, 2022, 9:46 a.m. UTC | #4 
Hi Georgi,

On Mon Jul 18, 2022 at 9:58 AM CEST, Georgi Djakov wrote:
> On 25.05.22 17:44, Luca Weiss wrote:
> > Add all the different NoC providers that are found in SM6350 and
> > populate different nodes that use the interconnect properties.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> > Changes since v2:
> > * none
> > 
> >   arch/arm64/boot/dts/qcom/sm6350.dtsi | 109 +++++++++++++++++++++++++++
> >   1 file changed, 109 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > index fb1a0f662575..119073f19285 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > @@ -1,11 +1,13 @@
> >   // SPDX-License-Identifier: BSD-3-Clause
> >   /*
> >    * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> > + * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
> >    */
> >   
> >   #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> >   #include <dt-bindings/clock/qcom,rpmh.h>
> >   #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interconnect/qcom,sm6350.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/mailbox/qcom-ipcc.h>
> >   #include <dt-bindings/power/qcom-rpmpd.h>
> > @@ -539,6 +541,10 @@ i2c0: i2c@880000 {
> >   				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> > +						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> > +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> >   				status = "disabled";
> >   			};
> >   
> > @@ -552,6 +558,10 @@ i2c2: i2c@888000 {
> >   				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
> > +						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
> > +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> >   				status = "disabled";
> >   			};
> >   		};
> > @@ -578,6 +588,10 @@ i2c6: i2c@980000 {
> >   				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> >   				status = "disabled";
> >   			};
> >   
> > @@ -591,6 +605,10 @@ i2c7: i2c@984000 {
> >   				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> >   				status = "disabled";
> >   			};
> >   
> > @@ -604,6 +622,10 @@ i2c8: i2c@988000 {
> >   				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> >   				status = "disabled";
> >   			};
> >   
> > @@ -615,6 +637,9 @@ uart9: serial@98c000 {
> >   				pinctrl-names = "default";
> >   				pinctrl-0 = <&qup_uart9_default>;
> >   				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
> > +				interconnect-names = "qup-core", "qup-config";
> >   				status = "disabled";
> >   			};
> >   
> > @@ -628,11 +653,62 @@ i2c10: i2c@990000 {
> >   				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> >   				#address-cells = <1>;
> >   				#size-cells = <0>;
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> > +						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
> > +						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
> > +				interconnect-names = "qup-core", "qup-config", "qup-memory";
> >   				status = "disabled";
> >   			};
> >   
> >   		};
> >   
> > +		config_noc: interconnect@1500000 {
> > +			compatible = "qcom,sm6350-config-noc";
> > +			reg = <0 0x01500000 0 0x28000>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +		};
> > +
> > +		system_noc: interconnect@1620000 {
> > +			compatible = "qcom,sm6350-system-noc";
> > +			reg = <0 0x01620000 0 0x17080>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +
> > +			clk_virt: interconnect-clk-virt {
> > +				compatible = "qcom,sm6350-clk-virt";
> > +				#interconnect-cells = <2>;
> > +				qcom,bcm-voters = <&apps_bcm_voter>;
> > +			};
> > +		};
> > +
> > +		aggre1_noc: interconnect@16e0000 {
> > +			compatible = "qcom,sm6350-aggre1-noc";
> > +			reg = <0 0x016e0000 0 0x15080>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +		};
> > +
> > +		aggre2_noc: interconnect@1700000 {
> > +			compatible = "qcom,sm6350-aggre2-noc";
> > +			reg = <0 0x01700000 0 0x1f880>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +
> > +			compute_noc: interconnect-compute-noc {
> > +				compatible = "qcom,sm6350-compute-noc";
> > +				#interconnect-cells = <2>;
> > +				qcom,bcm-voters = <&apps_bcm_voter>;
> > +			};
> > +		};
> > +
> > +		mmss_noc: interconnect@1740000 {
> > +			compatible = "qcom,sm6350-mmss-noc";
> > +			reg = <0 0x01740000 0 0x1c100>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +		};
> > +
> >   		ufs_mem_hc: ufs@1d84000 {
> >   			compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
> >   				     "jedec,ufs-2.0";
> > @@ -933,6 +1009,10 @@ sdhc_2: sdhci@8804000 {
> >   				 <&gcc GCC_SDCC2_APPS_CLK>,
> >   				 <&rpmhcc RPMH_CXO_CLK>;
> >   			clock-names = "iface", "core", "xo";
> > +			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> > +					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> > +			interconnect-names = "sdhc-ddr", "cpu-sdhc";
> > +
> >   			qcom,dll-config = <0x0007642c>;
> >   			qcom,ddr-config = <0x80040868>;
> >   			power-domains = <&rpmhpd 0>;
> > @@ -947,11 +1027,15 @@ sdhc2_opp_table: sdhc2-opp-table {
> >   				opp-100000000 {
> >   					opp-hz = /bits/ 64 <100000000>;
> >   					required-opps = <&rpmhpd_opp_svs_l1>;
> > +					opp-peak-kBps = <790000 131000>;
> > +					opp-avg-kBps = <50000 50000>;
> >   				};
> >   
> >   				opp-202000000 {
> >   					opp-hz = /bits/ 64 <202000000>;
> >   					required-opps = <&rpmhpd_opp_nom>;
> > +					opp-peak-kBps = <3190000 294000>;
> > +					opp-avg-kBps = <261438 300000>;
>
> Just wondering where do these values come from? Are they from the downstream DT?
> The rest looks good to me.

Exactly, the values are part of downstream dtsi[0]. The docs for this
property are:
- qcom,msm-bus,vectors-KBps:
    Arrays of unsigned integers representing:
    * master-id
    * slave-id
    * arbitrated bandwidth in KBps
    * instantaneous bandwidth in KBps

The first two paths downstream are consolidated into one here, the third
downstream is the second one here.

[0] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-12.1.0_r0.15/qcom/lagoon.dtsi#3165

Hope that clears it up!
Regards
Luca

>
> Thanks,
> Georgi
>
> >   				};
> >   			};
> >   		};
> > @@ -1017,12 +1101,33 @@ dp_phy: dp-phy@88ea200 {
> >   			};
> >   		};
> >   
> > +		dc_noc: interconnect@9160000 {
> > +			compatible = "qcom,sm6350-dc-noc";
> > +			reg = <0 0x09160000 0 0x3200>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +		};
> > +
> >   		system-cache-controller@9200000 {
> >   			compatible = "qcom,sm6350-llcc";
> >   			reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
> >   			reg-names = "llcc_base", "llcc_broadcast_base";
> >   		};
> >   
> > +		gem_noc: interconnect@9680000 {
> > +			compatible = "qcom,sm6350-gem-noc";
> > +			reg = <0 0x09680000 0 0x3e200>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +		};
> > +
> > +		npu_noc: interconnect@9990000 {
> > +			compatible = "qcom,sm6350-npu-noc";
> > +			reg = <0 0x09990000 0 0x1600>;
> > +			#interconnect-cells = <2>;
> > +			qcom,bcm-voters = <&apps_bcm_voter>;
> > +		};
> > +
> >   		usb_1: usb@a6f8800 {
> >   			compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
> >   			reg = <0 0x0a6f8800 0 0x400>;
> > @@ -1051,6 +1156,10 @@ usb_1: usb@a6f8800 {
> >   
> >   			resets = <&gcc GCC_USB30_PRIM_BCR>;
> >   
> > +			interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
> > +					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
> > +			interconnect-names = "usb-ddr", "apps-usb";
> > +
> >   			usb_1_dwc3: usb@a600000 {
> >   				compatible = "snps,dwc3";
> >   				reg = <0 0x0a600000 0 0xcd00>;
Luca Weiss Aug. 12, 2022, 12:09 p.m. UTC | #5 
Hi Bjorn,

On Wed May 25, 2022 at 4:44 PM CEST, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>

The other patches (1-4) from this series have been merged into torvalds'
repo already, so just this one is missing from 5.20/6.0.

Could you please pick it up for the next merge window if everything's
alright with it?

Regards
Luca
Krzysztof Kozlowski Aug. 12, 2022, 1:34 p.m. UTC | #6 
On 12/08/2022 15:09, Luca Weiss wrote:
> Hi Bjorn,
> 
> On Wed May 25, 2022 at 4:44 PM CEST, Luca Weiss wrote:
>> Add all the different NoC providers that are found in SM6350 and
>> populate different nodes that use the interconnect properties.
>>
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> 
> The other patches (1-4) from this series have been merged into torvalds'
> repo already, so just this one is missing from 5.20/6.0.
> 
> Could you please pick it up for the next merge window if everything's
> alright with it?

It's still a merge window...

Best regards,
Krzysztof
Bjorn Andersson Aug. 29, 2022, 11:46 p.m. UTC | #7 
On Wed, 25 May 2022 16:43:56 +0200, Luca Weiss wrote:
> This series adds interconnect support for the various NoCs found on
> sm6350.
> 
> A more special modification is allowing child NoC devices, like done for
> rpm-based qcm2290 which was already merged, but now for rpmh-based
> interconnect.
> 
> [...]

Applied, thanks!

[5/5] arm64: dts: qcom: sm6350: Add interconnect support
      commit: 38c5c4fe17014130dee4f85e663c5d919655801e

Best regards,
Bjorn Andersson Aug. 29, 2022, 11:46 p.m. UTC | #8 
On Wed, 25 May 2022 16:44:01 +0200, Luca Weiss wrote:
> Add all the different NoC providers that are found in SM6350 and
> populate different nodes that use the interconnect properties.
> 
> 

Applied, thanks!

[5/5] arm64: dts: qcom: sm6350: Add interconnect support
      commit: 38c5c4fe17014130dee4f85e663c5d919655801e

Best regards,