| Message ID | 20220516100213.1536571-1-cyndis@kapsi.fi |
|---|---|
| Headers | show |
| Series | Host1x support on Tegra234 | expand |
On 16/05/2022 12:02, cyndis@kapsi.fi wrote: > From: Mikko Perttunen <mperttunen@nvidia.com> > > Add device tree nodes for Host1x and VIC on Tegra234. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 46 ++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index cb3af539e477..cae68e59580c 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -454,6 +454,52 @@ misc@100000 { > status = "okay"; > }; > > + host1x@13e00000 { Generic node names, if that possible. Since the bindings do not exist in the next, I actually cannot figure out what's host1x... > + compatible = "nvidia,tegra234-host1x"; > + reg = <0x13e00000 0x10000>, > + <0x13e10000 0x10000>, > + <0x13e40000 0x10000>; > + reg-names = "common", "hypervisor", "vm"; > + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", > + "syncpt5", "syncpt6", "syncpt7", "host1x"; > + clocks = <&bpmp TEGRA234_CLK_HOST1X>; > + clock-names = "host1x"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0x15000000 0x15000000 0x01000000>; > + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; > + interconnect-names = "dma-mem"; > + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; > + > + vic@15340000 { The same... vic is usually a vectored interrupt controller, so this should be interrupt-controller. Unless it is something entirely else, so then you need to come with a generic name. Best regards, Krzysztof
On 5/17/22 11:01, Krzysztof Kozlowski wrote: > On 16/05/2022 12:02, cyndis@kapsi.fi wrote: >> From: Mikko Perttunen <mperttunen@nvidia.com> >> >> Add device tree nodes for Host1x and VIC on Tegra234. >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> --- >> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 46 ++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> index cb3af539e477..cae68e59580c 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> @@ -454,6 +454,52 @@ misc@100000 { >> status = "okay"; >> }; >> >> + host1x@13e00000 { > > Generic node names, if that possible. Since the bindings do not exist in > the next, I actually cannot figure out what's host1x... Host1x is a hardware block that provides programmable DMA channels, HW synchronization primitives, and virtualization support for IP blocks connected to its "host1x bus". So far I haven't found a one or two word way to describe it despite efforts. In any case, considering all the existing documentation and device trees that use this name, I'd prefer not changing it (especially as I don't know what else it could be called). > >> + compatible = "nvidia,tegra234-host1x"; >> + reg = <0x13e00000 0x10000>, >> + <0x13e10000 0x10000>, >> + <0x13e40000 0x10000>; >> + reg-names = "common", "hypervisor", "vm"; >> + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", >> + "syncpt5", "syncpt6", "syncpt7", "host1x"; >> + clocks = <&bpmp TEGRA234_CLK_HOST1X>; >> + clock-names = "host1x"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + ranges = <0x15000000 0x15000000 0x01000000>; >> + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; >> + interconnect-names = "dma-mem"; >> + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; >> + >> + vic@15340000 { > > The same... vic is usually a vectored interrupt controller, so this > should be interrupt-controller. Unless it is something entirely else, so > then you need to come with a generic name. VIC here is video image compositor (with various other 2d operations). I suppose I can invent some generic name. Any thoughts, Thierry? Mikko > > > Best regards, > Krzysztof
On 17/05/2022 10:38, Mikko Perttunen wrote: >>> >>> + host1x@13e00000 { >> >> Generic node names, if that possible. Since the bindings do not exist in >> the next, I actually cannot figure out what's host1x... > > Host1x is a hardware block that provides programmable DMA channels, HW > synchronization primitives, and virtualization support for IP blocks > connected to its "host1x bus". So far I haven't found a one or two word > way to describe it despite efforts. In any case, considering all the > existing documentation and device trees that use this name, I'd prefer > not changing it (especially as I don't know what else it could be called). OK Best regards, Krzysztof
On 5/16/22 13:02, cyndis@kapsi.fi wrote: > Hi all, > > This series adds support for Host1x and VIC on the recently released > Tegra234 (Orin) SoC. It's split into the following parts: > > * Device tree binding updates > * Cleanup in host1x driver > * Add programming of new registers and old registers that now need to > be programmed to a non-reset value > * Tegra234 device data and headers > * Rewrite of the job opcode sequence, and related patches to > support MLOCKs on Tegra186+. > > The rewrite of the job opcode sequence brings Tegra186, Tegra194 and > Tegra234 support to a 'full-featured' status that is necessary to > support all host1x features in the future. This should not have any > impact on older SoCs. > > This series should be applied on top of the Host1x context isolation > series. > > Tested on Jetson AGX Xavier and Jetson AGX Orin. The code looks okay at a quick glance. Please rebase the patches on top of latest -next. Perhaps won't hurt to merge all the related patchsets into a single series for 5.20.
On 6/3/22 12:38, Dmitry Osipenko wrote: > On 5/16/22 13:02, cyndis@kapsi.fi wrote: >> Hi all, >> >> This series adds support for Host1x and VIC on the recently released >> Tegra234 (Orin) SoC. It's split into the following parts: >> >> * Device tree binding updates >> * Cleanup in host1x driver >> * Add programming of new registers and old registers that now need to >> be programmed to a non-reset value >> * Tegra234 device data and headers >> * Rewrite of the job opcode sequence, and related patches to >> support MLOCKs on Tegra186+. >> >> The rewrite of the job opcode sequence brings Tegra186, Tegra194 and >> Tegra234 support to a 'full-featured' status that is necessary to >> support all host1x features in the future. This should not have any >> impact on older SoCs. >> >> This series should be applied on top of the Host1x context isolation >> series. >> >> Tested on Jetson AGX Xavier and Jetson AGX Orin. > > The code looks okay at a quick glance. Please rebase the patches on top > of latest -next. Perhaps won't hurt to merge all the related patchsets > into a single series for 5.20. > Thanks! Yeah, I'll rebase and resend the context isolation series and this next week. Mikko
From: Mikko Perttunen <mperttunen@nvidia.com> Hi all, This series adds support for Host1x and VIC on the recently released Tegra234 (Orin) SoC. It's split into the following parts: * Device tree binding updates * Cleanup in host1x driver * Add programming of new registers and old registers that now need to be programmed to a non-reset value * Tegra234 device data and headers * Rewrite of the job opcode sequence, and related patches to support MLOCKs on Tegra186+. The rewrite of the job opcode sequence brings Tegra186, Tegra194 and Tegra234 support to a 'full-featured' status that is necessary to support all host1x features in the future. This should not have any impact on older SoCs. This series should be applied on top of the Host1x context isolation series. Tested on Jetson AGX Xavier and Jetson AGX Orin. Thanks, Mikko Mikko Perttunen (13): dt-bindings: Add bindings for Tegra234 Host1x and VIC dt-bindings: Add headers for Host1x and VIC on Tegra234 arm64: tegra: Add Host1x and VIC on Tegra234 gpu: host1x: Deduplicate hardware headers gpu: host1x: Simplify register mapping and add common aperture gpu: host1x: Program virtualization tables gpu: host1x: Allow reset to be missing gpu: host1x: Program interrupt destinations on Tegra234 gpu: host1x: Tegra234 device data and headers gpu: host1x: Rewrite job opcode sequence gpu: host1x: Add MLOCK release code on Tegra234 gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+ drm/tegra: vic: Add Tegra234 support .../display/tegra/nvidia,tegra124-vic.yaml | 1 + .../display/tegra/nvidia,tegra20-host1x.yaml | 108 +++++++++-- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 46 +++++ drivers/gpu/drm/tegra/drm.c | 1 + drivers/gpu/drm/tegra/vic.c | 12 ++ drivers/gpu/host1x/Makefile | 3 +- drivers/gpu/host1x/cdma.c | 19 +- drivers/gpu/host1x/dev.c | 112 +++++++---- drivers/gpu/host1x/dev.h | 11 ++ drivers/gpu/host1x/hw/cdma_hw.c | 34 ++++ drivers/gpu/host1x/hw/channel_hw.c | 144 ++++++++------ drivers/gpu/host1x/hw/host1x01_hardware.h | 114 +---------- drivers/gpu/host1x/hw/host1x02_hardware.h | 113 +---------- drivers/gpu/host1x/hw/host1x04_hardware.h | 113 +---------- drivers/gpu/host1x/hw/host1x05_hardware.h | 113 +---------- drivers/gpu/host1x/hw/host1x06_hardware.h | 128 +------------ drivers/gpu/host1x/hw/host1x07_hardware.h | 128 +------------ drivers/gpu/host1x/hw/host1x08.c | 33 ++++ drivers/gpu/host1x/hw/host1x08.h | 15 ++ drivers/gpu/host1x/hw/host1x08_hardware.h | 21 ++ drivers/gpu/host1x/hw/hw_host1x08_channel.h | 11 ++ drivers/gpu/host1x/hw/hw_host1x08_common.h | 11 ++ .../gpu/host1x/hw/hw_host1x08_hypervisor.h | 9 + drivers/gpu/host1x/hw/hw_host1x08_uclass.h | 181 ++++++++++++++++++ drivers/gpu/host1x/hw/hw_host1x08_vm.h | 36 ++++ drivers/gpu/host1x/hw/intr_hw.c | 11 ++ drivers/gpu/host1x/hw/opcodes.h | 150 +++++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 4 + include/dt-bindings/memory/tegra234-mc.h | 5 + .../dt-bindings/power/tegra234-powergate.h | 1 + include/dt-bindings/reset/tegra234-reset.h | 1 + 31 files changed, 877 insertions(+), 812 deletions(-) create mode 100644 drivers/gpu/host1x/hw/host1x08.c create mode 100644 drivers/gpu/host1x/hw/host1x08.h create mode 100644 drivers/gpu/host1x/hw/host1x08_hardware.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_channel.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_common.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_uclass.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x08_vm.h create mode 100644 drivers/gpu/host1x/hw/opcodes.h