| Message ID | 20220413103356.3433637-1-abel.vesa@nxp.com |
|---|---|
| Headers | show |
| Series | arm64: dts: Add i.MX8DXL initial support | expand |
On Wed, Apr 13, 2022 at 01:33:46PM +0300, Abel Vesa wrote: > From: Jacky Bai <ping.bai@nxp.com> > > On i.MX8DXL, the Connectivity subsystem includes below peripherals: > 1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG, > 1x eMMC, 2x SD, 1x NAND. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> I got following warning with 'W=1' build flag. ../arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi:10.45-15.4: Warning (simple_bus_reg): /bus@5b000000/clock-conn-enet0-root: missing or empty reg/ranges property ../arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi:63.29-68.4: Warning (simple_bus_reg): /bus@5b000000/usbphy@0x5b110000: simple-bus unit address format error, expected "5b110000" ../arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi:7.27-12.4: Warning (simple_bus_reg): /bus@5c000000/clock-db-ipg: missing or empty reg/ranges property Shawn > --- > .../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 134 ++++++++++++++++++ > 1 file changed, 134 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi > new file mode 100644 > index 000000000000..b776d0ed42b4 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi > @@ -0,0 +1,134 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019-2021 NXP > + */ > + > +/delete-node/ &enet1_lpcg; > +/delete-node/ &fec2; > + > +&conn_subsys { > + conn_enet0_root_clk: clock-conn-enet0-root { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <250000000>; > + clock-output-names = "conn_enet0_root_clk"; > + }; > + > + eqos: ethernet@5b050000 { > + compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; > + reg = <0x5b050000 0x10000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eth_wake_irq", "macirq"; > + clocks = <&eqos_lpcg IMX_LPCG_CLK_2>, > + <&eqos_lpcg IMX_LPCG_CLK_4>, > + <&eqos_lpcg IMX_LPCG_CLK_0>, > + <&eqos_lpcg IMX_LPCG_CLK_3>, > + <&eqos_lpcg IMX_LPCG_CLK_1>; > + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; > + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <125000000>; > + power-domains = <&pd IMX_SC_R_ENET_1>; > + status = "disabled"; > + }; > + > + usbotg2: usb@5b0e0000 { > + compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb"; > + reg = <0x5b0e0000 0x200>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; > + fsl,usbphy = <&usbphy2>; > + fsl,usbmisc = <&usbmisc2 0>; > + /* > + * usbotg1 and usbotg2 share one clock > + * scfw disable clock access and keep it always on > + * in case other core (M4) use one of these. > + */ > + clocks = <&clk_dummy>; > + ahb-burst-config = <0x0>; > + tx-burst-size-dword = <0x10>; > + rx-burst-size-dword = <0x10>; > + #stream-id-cells = <1>; Where do I find bindings for this property? Shawn > + power-domains = <&pd IMX_SC_R_USB_1>; > + status = "disabled"; > + }; > + > + usbmisc2: usbmisc@5b0e0200 { > + #index-cells = <1>; > + compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc"; > + reg = <0x5b0e0200 0x200>; > + }; > + > + usbphy2: usbphy@0x5b110000 { > + compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; > + reg = <0x5b110000 0x1000>; > + clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>; > + status = "disabled"; > + }; > + > + eqos_lpcg: clock-controller@5b240000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x5b240000 0x10000>; > + #clock-cells = <1>; > + clocks = <&conn_enet0_root_clk>, > + <&conn_axi_clk>, > + <&conn_axi_clk>, > + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, > + <&conn_ipg_clk>; > + clock-indices = <IMX_LPCG_CLK_0>, > + <IMX_LPCG_CLK_2>, > + <IMX_LPCG_CLK_4>, > + <IMX_LPCG_CLK_5>, > + <IMX_LPCG_CLK_6>; > + clock-output-names = "eqos_ptp", > + "eqos_mem_clk", > + "eqos_aclk", > + "eqos_clk", > + "eqos_csr_clk"; > + power-domains = <&pd IMX_SC_R_ENET_1>; > + }; > + > + usb2_2_lpcg: clock-controller@5b280000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x5b280000 0x10000>; > + #clock-cells = <1>; > + clock-indices = <IMX_LPCG_CLK_7>; > + clocks = <&conn_ipg_clk>; > + clock-output-names = "usboh3_2_phy_ipg_clk"; > + }; > +}; > + > +&enet0_lpcg { > + clocks = <&conn_enet0_root_clk>, > + <&conn_enet0_root_clk>, > + <&conn_axi_clk>, > + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, > + <&conn_ipg_clk>, > + <&conn_ipg_clk>; > +}; > + > +&fec1 { > + compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec"; > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; > + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; > + assigned-clock-rates = <125000000>; > +}; > + > +&usdhc1 { > + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > +}; > + > +&usdhc2 { > + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; > +}; > + > +&usdhc3 { > + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > +}; > -- > 2.34.1 >
On Wed, Apr 13, 2022 at 01:33:49PM +0300, Abel Vesa wrote: > From: Jacky Bai <ping.bai@nxp.com> > > Add i.MX8DXL EVK board support. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 266 ++++++++++++++++++ > 2 files changed, 267 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 85c2c9ba5110..d6be4e8ff3c2 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -98,6 +98,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb Out of alphabetical order. > dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts > new file mode 100644 > index 000000000000..68dfe722af6d > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts > @@ -0,0 +1,266 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019-2021 NXP > + */ > + > +/dts-v1/; > + > +#include "imx8dxl.dtsi" > + > +/ { > + model = "Freescale i.MX8DXL EVK"; > + compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; > + > + chosen { > + stdout-path = &lpuart0; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0 0x40000000>; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + /* > + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 > + * Shouldn't be used at A core and Linux side. > + * > + */ > + m4_reserved: m4@88000000 { > + no-map; > + reg = <0 0x88000000 0 0x8000000>; > + }; > + > + /* global autoconfigured region for contiguous allocations */ > + linux,cma { > + compatible = "shared-dma-pool"; > + reusable; > + size = <0 0x14000000>; > + alloc-ranges = <0 0x98000000 0 0x14000000>; > + linux,cma-default; > + }; > + }; > + > + reg_usdhc2_vmmc: usdhc2-vmmc { > + compatible = "regulator-fixed"; > + regulator-name = "SD1_SPWR"; > + regulator-min-microvolt = <3000000>; > + regulator-max-microvolt = <3000000>; > + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + off-on-delay-us = <3480>; > + }; > +}; > + > +&lpuart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart0>; > + status = "okay"; > +}; > + > +&lpuart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart1>; > + status = "okay"; > +}; > + > +&lsio_gpio4 { > + status = "okay"; > +}; > + > +&lsio_gpio5 { > + status = "okay"; > +}; > + > +&thermal_zones { > + pmic-thermal0 { > + polling-delay-passive = <250>; > + polling-delay = <2000>; > + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; Newline between properties and child node. > + trips { > + pmic_alert0: trip0 { > + temperature = <110000>; > + hysteresis = <2000>; > + type = "passive"; > + }; Newline between nodes. > + pmic_crit0: trip1 { > + temperature = <125000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + cooling-maps { > + map0 { > + trip = <&pmic_alert0>; > + cooling-device = > + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + bus-width = <8>; > + no-sd; > + no-sdio; > + non-removable; > + status = "okay"; One level indent is good enough. Shawn > +}; > + > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + bus-width = <4>; > + vmmc-supply = <®_usdhc2_vmmc>; > + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; > + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; > + max-frequency = <100000000>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog>; > + > + pinctrl_hog: hoggrp { > + fsl,pins = < > + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 > + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 > + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c > + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 > + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 > + >; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 > + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 > + >; > + }; > + > + pinctrl_lpuart0: lpuart0grp { > + fsl,pins = < > + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 > + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 > + >; > + }; > + > + pinctrl_lpuart1: lpuart1grp { > + fsl,pins = < > + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 > + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 > + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 > + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 > + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 > + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 > + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 > + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 > + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 > + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 > + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 > + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 > + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 > + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 > + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 > + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 > + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 > + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 > + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 > + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 > + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 > + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 > + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 > + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 > + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 > + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 > + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 > + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 > + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 > + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 > + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 > + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 > + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 > + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ > + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ > + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 > + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 > + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { > + fsl,pins = < > + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 > + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 > + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { > + fsl,pins = < > + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 > + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 > + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 > + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 > + >; > + }; > +}; > -- > 2.34.1 >