[v4,0/2] new emtrion hardware emCON-MX8M Mini

From: Reinhold Mueller <reinhold.mueller@emtrion.com>

This patchset adds support for the emtrion emCON-MX8M Mini

Changes

v4:
[PATCH 1/2]
	- no fixes, already Acked-by: Rob Herring <robh@kernel.org>
[PATCH 2/2]
	- removed reserved memory nodes
	- added a child node in fec for the phy reset gpios

v3:
[PATCH 1/2]
	- no fixes, Acked-by: Rob Herring <robh@kernel.org>
[PATCH 2/2]
	- inserted hyphen in some node names
	- spell out regulator in some regulator nodes
	- order of properties
	- sort label node alphabetically
	- inserting space before node name

v2:
[PATCH 1/2]
	- no fixes
[PATCH 2/2]
	- replaced GPIO_ACTIVE_LOW by IRQ_TYPE_LEVEL_LOW

v1:
[PATCH 0/2]
	- split former patch in dts -and yaml patches
[PATCH 1/2]
	- removing character '\t'
[PATCH 2/2]
	- correct entry compatible in spi-flash@0

Reinhold Mueller (2):
  dt-bindings: arm: Add emtrion hardware emCON-MX8M Mini
  arm64: dts: imx8mm: Add support for emtrion emCON-MX8M Mini

 .../devicetree/bindings/arm/fsl.yaml          |   1 +
 arch/arm64/boot/dts/freescale/Makefile        |   3 +-
 .../boot/dts/freescale/imx8mm-emcon-avari.dts |  23 +
 .../dts/freescale/imx8mm-emcon-avari.dtsi     | 139 ++++
 .../boot/dts/freescale/imx8mm-emcon.dtsi      | 626 ++++++++++++++++++
 5 files changed, 791 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi

Hi Reinhold,

On Mon, Dec 20, 2021 at 4:23 AM <reinhold.mueller@emtrion.com> wrote:

> +       pinctrl_ecspi1: ecspi1-grp {
> +               fsl,pins = <
> +                       MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x82
> +                       MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x82
> +                       MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x82
> +               >;
> +       };
> +
> +       pinctrl_ecspi1_cs: ecspi1-cs {
> +               fsl,pins = <
> +                       MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x40000
> +                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40000

This version looks good to me.

One nit: you seem to use a single SPI chipselect, but you add two entries here.

Is the MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 needed too?

Either way:

Reviewed-by: Fabio Estevam <festevam@gmail.com>

Hi Fabio,

thanks for the fast feedback.
Below i have commented your issue for clarification.

Regards
Reinhold


Reinhold Mueller
Software engineer


emtrion GmbH
Am Hasenbiel 6 | 76297 Stutensee | Germany

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> -----Ursprüngliche Nachricht-----
> Von: Fabio Estevam <festevam@gmail.com>
> Gesendet: Dienstag, 21. Dezember 2021 01:06
> An: Mueller, Reinhold <Reinhold.Mueller@emtrion.de>
> Cc: Rob Herring <robh+dt@kernel.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Sascha Hauer <kernel@pengutronix.de>;
> Shawn Guo <shawnguo@kernel.org>; NXP Linux Team <linux-
> imx@nxp.com>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
> BINDINGS <devicetree@vger.kernel.org>; linux-kernel <linux-
> kernel@vger.kernel.org>
> Betreff: Re: [PATCH v4 2/2] arm64: dts: imx8mm: Add support for emtrion
> emCON-MX8M Mini
>
> Hi Reinhold,
>
> On Mon, Dec 20, 2021 at 4:23 AM <reinhold.mueller@emtrion.com> wrote:
>
> > +       pinctrl_ecspi1: ecspi1-grp {
> > +               fsl,pins = <
> > +                       MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x82
> > +                       MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x82
> > +                       MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x82
> > +               >;
> > +       };
> > +
> > +       pinctrl_ecspi1_cs: ecspi1-cs {
> > +               fsl,pins = <
> > +                       MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x40000
> > +                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40000
>
> This version looks good to me.
>
> One nit: you seem to use a single SPI chipselect, but you add two entries
> here.
>
> Is the MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 needed too?
Yes, of course the emCON provides a connector connecting two slaves on the spi bus.
>
> Either way:
>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

Hi Reinhold,

On Tue, Dec 21, 2021 at 4:33 AM Mueller, Reinhold
<Reinhold.Mueller@emtrion.de> wrote:

> Yes, of course the emCON provides a connector connecting two slaves on the spi bus.

In this case, then please pass gpio5 13 to the cs-gpios property too.